Silicon Valley Designers Council Chapter Meeting Oct. 13


Reading time ( words)

Join the Silicon Valley IPC Designers Council at TTM San Jose for an educational "Lunch 'n Learn" meeting on October 13 from 11:30 am to 1:30 pm. Speaker Julie Ellis, field applications engineer with TTM Technologies, will discuss “Printed Circuit Board Cost-Adders.”

A designer is faced with many challenges when planning their printed circuit board to achieve a balance of performance, quality and reliability versus cost. Unfortunately, the cost of a printed circuit board increases with size, thickness, number of layers, features, and technical difficulty.

Throughout this presentation, Julie will discuss basic design guidelines for standard production—as opposed to advanced capabilities—and how they affect the number of required processes and, therefore, cost. She will also discuss costs related to material utilization, fixed premiums for smaller lines/spaces and tolerances, and variable costs of high speed materials, drilling, and multiple lamination cycles. Lastly, Julie will show increasingly complex stack-ups to demonstrate how cost factors relate to the additional processes. You will learn the correlation between requirements and costs to help you make better design choices.

To RSVP, click here.

Location:
TTM San Jose
340 Turtle Creek Court
San Jose, CA  95125

Share


Suggested Items

Rigid-flex Design Tips and Best Practices

04/10/2017 | Craig Armenti, Mentor Graphics
While the traditional “design-separately-then-assemble” approach minimized potential issues with the flex portions of the product, it also had several inherent disadvantages. These include the cost associated with the physical connectors; the space required for the physical connectors; the need to properly manage interconnects that have to transition between the separate rigid and flex PCBs (through the connectors); and, of course, the time and cost associated with assembly. The move to the current generation of rigid-flex technology mitigates these issues; however, they are replaced with a different set of challenges and concerns.

TTM SJ Hosts IPC Designers Council Meeting

11/07/2016 | IPC
The Silicon Valley Chapter of the IPC Designers Council was treated to a delicious barbecue lunch on October 13 at TTM’s San Jose facility. About 20 PCB designers and support professionals gathered for the tri-tip lunch-n-learn conference.

Beyond Design: The Need for Speed—Strategies for Design Efficiency

05/02/2016 | Barry Olney, In-Circuit Design
Years of experience with one EDA tool obviously develops efficiency, whether the tool be high-end feature-packed or basic entry-level. And one becomes accustomed to the intricacies of all the good and bad features of their PCB design tool. However, there comes a time when one should really consider a change for the better to incorporate the latest methodologies. This month, I will look at productivity issues that impede the PCB design process.



Copyright © 2018 I-Connect007. All rights reserved.