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To deploy features commonly found in modern electronic products, such as high-fidelity audio, rich graphics, high-resolution displays, and wireless interfaces, designers must work with processors and FPGAs that use high-speed, high-bandwidth DDR memory.
But working with DDR interfaces poses unique design challenges. How do you know what component placement and routing are best or what constraints are needed to ensure your end products will work? This 15-minute on-demand PADS webinar explores the DDR memory interface and shows how an easy-to-use wizard can help you manage DDR issues during design.
To watch this webinar, click here.
Andy Shaughnessy, Design007 Magazine
During DesignCon 2018, I spoke with Tarun Amla, the executive vice president and CTO of ITEQ. We discussed ITEQ’s future plans, including the development of materials for cutting-edge technology needs, such as autonomous and electric vehicles, as well as 5G technology.
Real Time with...IPC
European Editor Pete Starkey and Ucamco partner Luc Maesen discuss Ucamco's newest solutions for PCB designers and fabricators, YELO (Yield Enhancing Layout Optimizer) and Communic8tor. Both of these products were recently launched for users in the North American market.
Real Time with DesignCon
SiSoft President and CTO Barry Katz sat down with Editor Andy Shaughnessy to share his thoughts on the company's papers presented during DesignCon 2018, as well as SiSoft's latest products and plans for 2018.