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The SMTA and Chip Scale Review have announced the program for the 14th annual International Wafer-Level Packaging Conference. The IWLPC will be held October 24-26, 2017 at the DoubleTree Hotel in San Jose, California.
The technical sessions on Tuesday and Wednesday are organized into three tracks: Wafer-Level Packaging, 3D Packaging, and Advanced Manufacturing and Test. The Wafer-Level Packaging (WLP) track features sessions on materials, processes, design, and new technology like Fan-Out WLP. The 3D Packaging track features sessions on Heterogeneous Integration Enablement, materials and equipment, processing technologies, and Smart System Integration and Applications. The Advanced Manufacturing and Test track features sessions on test, productivity, inspection, and metrology.
Subramanian Iyer, Ph.D., Distinguished Chancellor's Professor, Electrical Engineering Department, University of California, Los Angeles is scheduled to give the keynote presentation on the first day of the conference on “Packaging without the Package: A More Holistic Moore's Law.”
Richard (Kwang Wook) Bae, Vice President, Corporate Strategy & Planning, Samsung Electro-Mechanics, will deliver the keynote presentation in the morning of the second day, entitled "Samsung's FOPLP: Beyond Moore.”
Han Byung Joon, Ph.D., Chief Executive Officer, STATS ChipPAC is scheduled to give the keynote presentation in the evening on the second day of the conference on “Innovative Packaging Technologies Usher in a New Era for Integration Solutions.”
Packaging technology experts John Lau, Ph.D., ASM Pacific Technology; John Hunt, ASE (US) Inc.; Fernando Roa, Ph.D., Amkor Technology; and Rao Tummala, Ph.D., Georgia Institute of Technology, are scheduled to lead half-day workshops on Thursday, October 26, 2017.
Registration for IWLPC is now available online. Visit www.iwlpc.com for more information.