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The temporary or quick turn part is a reality in today’s fast-moving design process. In many cases, a search of the corporate library comes up short and you need to explore the supply chain for that perfect part. Starting a design with an unapproved or temporary part is a common occurrence in today’s design environment. This reality has forced all of us to adopt policies and procedures that allow for the use of temporary parts. The biggest challenge with temporary parts is making sure that all of the design’s components have been validated and all remnants of the temporary parts have been successfully purged or converted to an approved part.
Attendees will learn best practices for using and managing temporary parts in a design process. Watch a live demonstration using a design data management system and learn how to prevent a temporary part from slipping through the release process and into manufacturing, all while you track and manage parts throughout the design cycle.
December 6, 2017 2 pm Eastern Time
For more information or to register, click here.
Bob Potock, Zuken
A new generation of 3D multiboard product-level design tools offer major improvements by managing multiboard placement in both 2D and 3D, and enabling co-design of the chip, package and board in a single environment. Multiboard design makes it possible to create and validate a design with any combination of system-on-chips (SOCs), packages, and PCBs as a complete system. Chip-package-board co-design enables designers to optimize routability via pin assignment and I/O placement to minimize layer counts between the package, chip and board. The new design methodology makes it possible to deliver more functional, higher performing and less expensive products to market in less time.
Andy Shaughnessy, I-Connect007
For our multi-board design issue, I interviewed Dave Wiens, product marketing manager for Mentor, a Siemens business. We discussed how the multi-board design technique differs from laying out single boards, along with the planning, simulation and analysis processes required to design multi-board systems.
Chang Fei Yee, Keysight Technologies
This article briefly introduces the 4-level pulse amplitude modulation (PAM-4) and its application in 400 Gigabit Ethernet (400GbE), to support the booming data traffic volume in conjunction with the deployment of 5G mobile communications. Furthermore, this article also highlights the essential pre-layout effort from signal integrity perspective for physical (PHY) link design on a PCB, including material selection, transmission line design and channel simulation to support 56Gbps data rate that paves the way for seamless communication in 400GbE.