Designers Notebook: Strategies for High-Density PCBs

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As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as high-density interconnect (HDI) processing. The primary driver for HDI is the increased complexity of the more advanced semiconductor package technology. These differences can be greater than one order of magnitude in interconnection density.

Semiconductor Packaging

Although the development of array-configured packaging for ICs has alleviated circuit routing difficulty somewhat, product miniaturization and performance goals are not easily achieved. To further complicate the PCB design process, many companies furnishing multiple die or multi-functional semiconductor packaging are forced to significantly increasing I/O while reducing both contact size and pitch. This higher I/O and finer pitch evolution is due in part to the OEM need for more capability in an ever-shrinking space. Further complicating traditional PCB design, some companies are doing away with some or all traditional semiconductor packaged semiconductors.

System-in-package (SiP), for example, whether die stack or package-on-package, has rapidly penetrated most major market segments. This includes consumer electronics, mobile, automotive, computing, networking, communications, and medical electronics. The benefits of SiP will differ for various market segments but they can share some very common elements: shorter time to market, smaller size and lower cost. Area efficiency (more functionality in a single package footprint) has resulted in the strongest initial penetration in consumer electronics. These mixed-function SiP solutions have become commonplace in small form factor systems, such as mobile phones, memory cards, and other portable electronics products and the number has been increasing rapidly.

In contrast, it has become common for developers to procure bare, uncased die elements that are configured for face-down (flip-chip) mounting. Although flip-chip was originally considered for relatively low I/O die, the redistribution of the peripheral located contact sites to a more uniform area array format has enabled the commercial use of larger and much higher I/O die elements. Regarding flip-chip mounting, interconnection from die element to the PCB is commonly achieved with alloy bumps, spheres or, for very fine pitch applications, raised copper pillar contacts that, although very small, are compatible with a conventional reflow soldering processes.

To read this entire article, which appeared in the November 2017 issue of The PCB Design Magazine, click here.



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