-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLevel Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
Robert Hanson to Present at Cascade DC Chapter Meeting Sept. 18
September 12, 2019 | IPC Designers CouncilEstimated reading time: 1 minute
Be sure to sign up for the upcoming IPC Designers Council Cascade Chapter seminar on September 18, 2019 at Lake Washington Institute of Technology. Americom Seminars President Robert Hanson, a veteran high-speed design instructor, will present "Differential Signaling: Tradeoffs for Optimization of Signal Quality and Routing.” This evening event is free and dinner will be provided, courtesy of Cadence Design Systems. Don't miss out on this great educational opportunity to advance your knowledge and design skills.
During this seminar, attendees will learn about the attributes of loosely/tightly coupled differential pairs, as well as definitions and examples of differential-mode and common-mode voltage, current and differential impedance, both odd and even modes. The advantages and disadvantages of edge (side-by-side), broadside (dual), asymmetric and microstrip differentials will also be discussed.
Pertinent topics regarding reflections and crosstalk in differentials will be included. Metastability, clock skew, driver skew, bit pattern sensitivity, ISI, skin effect, dielectric constant, jitter, BER, and the eye diagram are part of the session. Other topics that will be discussed include matching electrical lengths, differential unbalance, controlling Zo, differential/common mode radiation, transversing connectors, and other signal quality issues and design guides.
Attendees will learn:
- All voltage, impedance, and current definitions for differential signaling.
- Comparison of edge, broadside, asymmetric, and microstrip differential layouts and effectiveness in controlling crosstalk and radiated emissions.
- How to overcome differential unbalance.
- How to control Zo when switching from loosely coupled to tightly coupled (and vice versa) differential layouts.
- The major drawback when using broadside differentials.
- Why differential signaling is essential for long haul, high-speed transmission lines.
To sign up, please go to our website: http://cascade-ipcdc.org
Meeting Agenda
5:45 pm to 6:00 pm: Dinner is served
6:00 pm to 8:30 pm: Presentation
8:30 pm to 8:40 pm: Q&A
8:40 pm to 8:45 pm: Door prize drawings
Next Chapter meeting: December 4, 2019
Tim Mullin, President
IPC Designers Council - Cascade Chapter
http://cascade-ipcdc.org
Cell: (253) 229-6914
Suggested Items
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.