Beyond Design: The Curse of the Golden Board

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At DC and low frequencies, the inductance of transmission line paths can be ignored. However, as the frequency and rise time increase, we soon realize that the multilayer PCB is not an ideal environment to transfer high-speed data. Here, parasitic capacitance and inductance plague the most basic of designs. Inductance, in particular, impacts on virtually all signal and power integrity issues.

To optimize the physical layout for acceptable performance, inductance must be minimized:

  1. The mutual inductance between signal paths intensifies switching noise
  2. The inductance of the power distribution network (PDN) bypass and decoupling capacitors dramatically affects product performance and reliability
  3. The effective loop inductance of the return current paths impacts on electromagnetic (EM) emissions

By understanding how the physical PCB layout influences the degree of inductance, PCB designers can triumph over their arch-enemy.

Electric fields and magnetic fields play an equal role in moving energy in a multilayer PCB. EM fields also move energy in free space, but not at DC. The presence of voltage implies that there is an electric field, and the changing of that electric field creates a magnetic field. What may not be appreciated is that moving a voltage between two components requires moving energy (not a signal), which requires the existence of both electric and magnetic fields. When energy is not moving, the magnetic field is zero.

1. Mutual Inductance Between Signal Paths

When current flows in a conductor, there is a magnetic field. When a second conductor, carrying current, is brought into close proximity, there is a force between the two. If both currents flow in the same direction, then they are additive (think two parallel trace segments). When the currents flow in the opposite direction (think a trace over a return plane), the currents cancel. This implies that two individual traces should be kept well apart to reduce crosstalk whilst a signal trace should be tightly coupled to its return path (plane) to increase coupling and reduce inductance.

Parasitic inductance is often an afterthought in high-speed design. A substrate consisting of conducting and dielectric materials will have some parasitic inductance, possibly leading to problems like crosstalk, induced currents, noise coupling, and other effects that degrade signal quality.

Unfortunately, parasitic capacitance and inductance in a PCB are unavoidable. A PCB is composed of a number of parallel conducting elements that are separated by an insulator, basically forming a capacitor. Likewise, conductors on a PCB will inevitably form complete loops, creating an equivalent inductor. While making dielectric layers in the stackup thinner will decrease the loop area and the parasitic inductance, it will also increase parasitic capacitance. Therefore, one needs to choose the sweet spot where inductance is minimized, and capacitance is maximized.

In high-speed digital applications where multiple data lines can run at tens of Gbps, parasitic capacitance and inductance can produce impedance mismatch along the signal path. Any mismatch caused by parasitics will produce reflections along the transmission line, ultimately increasing timing jitter and bit error rates.

To read this entire column, which appeared in the August 2019 issue of Design007 Magazine, click here.



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