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This webinar will explore a predictive, productive and insightful workflow to get to an optimal DDR5 design that performs to the target speed grade, reliably.
DDR5 is the latest generation of memory in development, doubling the peak data rate to 6400 MT/s (compared to DDR4). With great technical ambitions come much tighter specifications for system PCB designers, especially when faced with channel loss, skew, reflections and crosstalk, all of which become much more significant at higher frequencies. In fact, PCB design margins are so minimal that DDR5 introduces equalization on the commodity DRAM chips for the first time.
The presentation will begin with pre-layout simulation to explore design choices, then transition to constraint-based high-speed routing in Zuken CR-8000. The design will then be verified by electromagnetic simulation and system simulations in order to build confidence in the final DDR5 design.
November 13, 2 PM EST
To register for this event, or for more information, click here.