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To better meet their performance and miniaturization goals, manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. This capability has been stimulated by the rapid deployment of new semiconductor packaging methodologies from a broad number of both domestic and offshore companies that understand that new product time-to-market can be the difference between leading and following.
The key enablers for providing interconnect for these new generations of multifunction semiconductor elements is choosing the best package substrate or interposer structure for the specific application. PCB designers will realize that the base material and interconnect metalization processes utilized for the traditional multilayer glass-epoxy component mounting base materials are very different from base materials common to semiconductor fabrication. Furthermore, the design rules for via formation and circuit geometry will have a significant difference. On the other hand, these high-density semiconductor package platforms are essentially miniature printed circuits requiring the same tools and skills developed for PCB design.
The following describes examples of both mature and evolving single-die package variations:
• Single-die ball grid array (BGA) and fine-pitch BGA (FBGA) packaging
• Die size and flip-chip package technologies
• Fan-in wafer-level packaging (FIWLP)
• Fan-out wafer-level packaging (FOWLP)
Single-die BGA and the FBGA package families commonly rely on either traditional faceup wire-bond or facedown flip-chip processing for interconnecting to a package substrate. The substrate is designed to redistribute the die terminals on the top surface of the package substrate to a PCB-compatible array contact pattern on the bottom surface. The die elements mounted onto the top surface will be coated or molded over with a polymer composition, and for board-level assembly, alloy spheres or bumps are furnished on the bottom surface.
Die-size BGA (DSBGA) generally adopts the die face-down approach. The interface between die and interposer may utilize flip-chip processing, but wire-bond and lead-bond processing are more common. A good example of the die-size package using a wire-bond interface is the center-bond memory family of products illustrated in Figure 1.
To read this entire column, which appeared in the January 2020 issue of Design007 Magazine, click here.