Achieving Fine Lines and Spaces, Part 1

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Circuit designs with three-mil lines and spaces are increasingly becoming the norm for high-layer multilayer fabrication and IC substrate technology. Regardless of one’s technology level, optimizing the imaging process should be of paramount concern. Over the next few months, I will present the critical steps in the imaging process and again provide insight as to where potential yield reducing defects can occur and how to prevent them. This month I will first approach the all-important surface preparation step prior to resist lamination.

Getting Surface Preparation Right

Consider the job that the photoresist must accomplish. Besides the fact that it must provide the optimum photospeed and the highest resolution, the resist must adhere to the copper surface in order prevent resist lifting during the developing and etching steps. How does one accomplish this? First, we have to get the surface preparation prior to resist lamination.

Now, consider the copper foil surface. For this particular column, we will focus on innerlayer copper foils rather than outer layers. For innerlayers, the fabricator must carefully prepare the copper surface in order to enhance the adhesion of the photoresist during the lamination process and prior to exposure and development. It is an accepted belief that resist adhesion to copper surface depends on two very critical factors:

• Overall cleanliness of the copper surface and
• Film contact area.

Read the full column here.


Editor's Note: This column originally appeared in the November 2013 issue of The PCB Magazine.

03/29/2023 | Andy Shaughnessy, Design007 Magazine

Andy Shaughnessy talks with John Andresakis about how the merger of resistive foil technologies from Ohmega and Ticer has evolved under the new ownership of Quantic. Andresakis also shares how these materials are finding new applications, especially in the embedded component application space, as the company reaches out to the new generation of PCB designers and design engineers.

03/16/2023 | Pete Starkey, I-Connect007

Widely believed to be the traditional Centre of England, Meriden was a popular venue for a gathering of the UK printed circuit community this month. They braved the forecast of heavy snow for the Institute of Circuit Technology’s annual general meeting to learn about current developments and challenges in a thought-provoking technical seminar and to network with industry peers and contemporaries. Thankfully, the forecasted heavy snowfall did not reach Meriden until after the event; we only had a few flurries, although the weather caused considerable disruption elsewhere in the country.

02/28/2023 | Pete Starkey, I-Connect007

Day 2 of the EIPC Winter Conference at the Groupama Stadium in the Décines-Charpieu region of the Metropolis of Lyon in eastern France included a privileged visit to the Bugey Nuclear Power Plant for those who were registered and passed their security clearance. Such was the interest that the party was split into morning and afternoon groups. EIPC board member Martyn Gaudion, CEO of Polar Instruments, made a fine job of moderating Session 6 twice over.