Matched Length Does Not Always Equal Matched Delay


Reading time ( words)

In previous columns, I have discussed matched length routing and how matched length does not necessarily mean matched delay. But, all design rules, specified by chip manufacturers regarding high-speed routing, specify matched length--not matched delay. In this month’s column we’ll take a look at the actual differences between the two.

Typically, more than one layer change is required when routing traces to matched length. Figure 1 illustrates the DDR2 address bus routing I did in Altium Designer, my preferred layout tool. In this case, each address signal has four layer changes. The red and green traces are the top and bottom layers--which should be kept as short as possible--and the yellow and orange traces are inner layers embedded between the planes. This was a particularly difficult route as there were two DDR2 memory chips placed on both the top and bottom sides of the board, so each address signal had to go to four different chips and still maintain the correct delay.

 Olney_Delay.jpg

Figure 1: Matched delay T-section DDR2 address routing in Altium Designer.

The longest routes should be placed on the inner layers as this reduces electromagnetic radiation. With all other factors being equal, generally, a trace routed on the inner stripline layer exhibits 4-10 dB less noise than a trace routed on the outer microstrip  layer. Also, please note that there are more high harmonics on the top layer routing. The high-frequency components radiate more readily because their shorter wavelengths are comparable to trace lengths, which act as antennas. Consequently, although the amplitude of the harmonic frequency components decreases as the frequency increases, the radiated frequency varies depending on the trace’s characteristics.

Read the full column here.


Editor's Note: This column originally appeared in the March 2014 issue of The PCB Design Magazine.

Share


Suggested Items

Martin Cotton Discusses Ventec’s New Book and Low-Loss Materials

04/11/2018 | Andy Shaughnessy, Design007 Magazine
During DesignCon 2018, Andy Shaughnessy sat down for an interview with Martin Cotton, director of OEM projects for Ventec. Martin was a PCB designer for years, so he has experience on both sides of the desk. They discussed Ventec’s reasons for coming to DesignCon, their expansion into low-loss materials, and Ventec’s new I-Connect007 book, The Printed Circuit Designer’s Guide to Thermal Management with Insulated Metal Substrates.

Mentor’s HyperLynx Automates SERDES Channel Design

04/09/2018 | Andy Shaughnessy, Design007 Magazine
Mentor recently released the newest version of its HyperLynx signal integrity software. This version may be the first SI tool in the industry to fully automate SERDES design channel validation. I spoke recently with Chuck Ferry, product marketing manager with Mentor, about the new HyperLynx and some of the new serial link design capabilities that customers have been demanding.

Part 2: EIPC’s 2018 Winter Conference in Lyon, Review of Day 1

02/19/2018 | Pete Starkey, I-Connect007
We continue with the rest of Pete Starkey’s report on Day 1 of the EIPC Winter Conference in Lyon, France. Included in this segment are presentations by Ventec, Ericsson, TTM and others, plus photos of their evening tour of Alstom.



Copyright © 2018 I-Connect007. All rights reserved.