Tin Whiskers, Part 5: Impact of Testing Conditions


Reading time ( words)

In this installment of the tin whisker series, we'll take a look at the impact of testing conditions, and follow-up with this statement from Part 4: “…all-encompassing tests to confirm or deny the culprits for tin whiskers are prohibitively costly and time-consuming…”

The JEDEC Solid State Technology Association (formerly known as the Joint Electron Device Engineering Council) has published several documents that address and/or are related to the testing of tin whiskers, which are good guidelines with which to start.

  • JEDEC Standard No. 201: Environmental Acceptance requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface Finishes.
  • JEDEC Standard No. 22A12: Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes.
  • JEDEC Standard No. 22-A104D: Temperature Cycling.

Primarily, three sets of testing conditions are included in the JEDEC documents: ambient temperature storage, elevated temperature storage and temperature cycling, with the following parameters:

Room  Temperature Humidity Storage
30 ± 2°C and 60 ± 3% RH
(1,000 hrs interval inspection/3,000 to 4,000 hours total duration)      

Temperature Humidity Unbiased
60 ± 5°C and 87 + 3/-2% RH
(1,000 hours interval inspection/3,000 to 4,000 hours total duration)      

Temperature Cycling
Lower end temperature: -55 to -40 (+0/-10)°C
Higher end temperature: +85 (+10/-0)°C
(500 cycles inspection /1,000 to 1,500 cycles duration/air to air/5 to 10 minute soak/three cycles per hour)

Read the full column here.


Editor's Note: This column originally appeared in the May 2014 issue of SMT Magazine.

Share

Print


Suggested Items

SMTA Europe Solder Finish Webinar Addresses Defects Causes and Cures

12/14/2020 | Pete Starkey, I-Connect007
“What is your most common PCB problem?” A survey conducted by Bob Willis had revealed finish solderability to be the predominant contender, and it was clear that the choice of solderable finish applied to surface mount boards could have a significant effect on the assembly yield and cost of the final circuit. SMTA Europe organised an informative and enlightening webinar this month entitled “Guide to PCB Solder Finishes—Process Defects Causes and Cures,” with soldering specialist Bob Willis as presenter.

Approaches to Overcome Nodules and Scratches on Wire-Bondable Plating on PCBs

07/17/2019 | Young K. Song and Vanja Bukva, Teledyne Dalsa Inc., and Ryan Wong, FTG Circuits
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. This paper details if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful.

Cavity Board SMT Assembly Challenges (Part 1)

06/26/2019 | By Dudi Amir and Brett Grossman, Intel Corp.
The concept behind Component-in-Cavity (CiC) is straightforward. If the tallest component(s) on the motherboard can be placed into a recession created in the motherboard, their thickness relative to the components on the surface of the PCB will thus effectively be reduced. While this concept may be straightforward, its implementation is not. That implementation is the focus of this paper. Read on.



Copyright © 2021 I-Connect007. All rights reserved.