Beyond Design: Embedded Signal Routing

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This article originally appeared in the September issue of PCB Magazine.

We hear all the time that one should avoid routing high-speed signals on the outer layers of a multilayer PCB. I myself preach this. Some say that this decreases radiation by up to 15 db. But, how much attenuation do we actually get from embedding the high-speed signals between the planes?

The four constraints to keep in mind:

1.         Keep the mark to space ration of the waveform equal as this eliminates all the even harmonics.

2.         Route high-speed signals out from the centre of the board where possible as any radiation will be in the opposite direction and will tend to cancel.

3.         Route high-speed signals between the planes, fanout out close to the driver (200MIL) dropping to an inner plane and route back up to the load again with a short fanout.

4.         Use the same reference plane for the return signals as this reduces the loop area and hence radiation.

Embedding signals between the planes also reduces susceptibility to radiation, as well as providing ESD protection. So, not only do we prevent noise from being radiated, but we also reduce the possibility of being affected by an external source.

Unfortunately, the high-frequency components of the fundamental (lowest frequency in a complex wave) radiate more readily because their shorter wavelengths are comparable to trace lengths, which act as antennas. Consequently, although the amplitude of the harmonic frequency components decreases as the frequency increases, the radiated frequency varies depending on the antennas/traces characteristics. Typically, the 5th and 7th harmonics radiate the most.

Also, studies conducted by Hewlett Packard have found that there is up to 20 dB greater emissions from edge-located traces compared to traces located in the centre of the board on outer layers. Yet, the same test performed on buried traces indicated no change as the traces were placed nearer the PCB edges. From this, we gather that it is best to keep well away from the edge of the board when routing on the outer layers. The impedance changes as the reference plane deceases in area beneath the trace.

In order to measure the difference in radiation between an embedded signal and a signal routed on an outer layer, I have ripped up a DDR2 design that I recently did. Of course, I try to avoid routing on the other layers so I will have to make a few changes to measure the effects.

Figure 1. The layout of the DDR2 section of the board.

As you can see from the design above, the routing is very dense with serpentine, matched length traces connecting the DDR2 memory to the CPU. DDR2 designs tend to radiate a fair bit anyway because of the close proximity of traces in a confined area.

Figure 2. The multilayer stackup.

The first thing to look at is the multilayer stackup. Characteristic impedance needs to be near 50 ohm and differential impedance around 100 ohms. The above is a very safe stackup, which I use all the time for this type of design. The impedance has been calculated by the ICD Stackup Planner (this can be downloaded from

Why safe? Each layer is embedded between two planes, reducing crosstalk from adjacent layers and providing a clear return path for the signals.

Figure 3. Very little routing is done on Layer 1 and 8 (outer layers).  Fanout, then straight down to the embedded planes.

Figure 4. Layers 3 and 6 contain all the DDR signals. The data lanes, strobes, address and command signals are matched to length constraints.

Figure 5. DDR MDQ5 layer 3. Data signals were re-routed on the outer (Top) layer. These signals are matched to 1.6 inch as per the previous connects.

Figure 6. The waveform of DQ5 looks a little noisy on the bottom, but the skew is still pretty good and there are no non-monotonic edges near the trigger levels.

Figure 7. The radiation of DQ5 is displayed above in the virtual Spectrum Analyzer.

The first red line (starting @ 40dB) is the FCC Class B limit (the most stringent for residential and small office environments). The blue line is the CISPR Class B limit. Above those are the Class B limits, which are more lenient for commercial environments. The third harmonic peaks at 46 dB just over the Class B limit. Currently, the FCC and CISPR limits only go up as far as 1 GHZ but we can measure the higher harmonics up to 10 GHz.

Also of concern, are the higher harmonics with 45.65 dB 4.595 GHz and 49.73 dB @ 6.76 GHz. This certainly would not pass the EMC test.

Let’s look now at the working design that actually passed the EMC. The original DQ5 trace is routed on the inner layer 3. As you can see, the fanout is very close to the driver and load so that the signal is almost totally embedded between the planes. In this case, we decided not to use series terminators (after pre-layout simulation) as the traces are short and it was not warranted.

Figure 8. DQ5 routed on inner layer 3.

Figure 9. Again, the DQ5 signal looks pretty normal on the virtual oscilloscope. Not so much noise this time on the bottom of the waveform.

Let’s make a comparison of the radiated noise. See Figure 10.

Figure 10. Radiated noise comparison.

As you can see (with all other factors being equal), in this case the trace routed on the inner layer 3 exhibits between 4 to 10 dB less noise then the trace routed on the top layer. Also, please note that there are more high harmonics on the top layer routing. The high-frequency components radiate more readily because their shorter wavelengths are comparable to trace lengths, which act as antennas. Consequently, although the amplitude of the harmonic frequency components decreases as the frequency increases, the radiated frequency varies depending on the traces characteristics.

In conclusion, routing high-speed signals embedded between the planes does reduce the radiated emissions by as much as 10 dB (in this case). Adding a series terminator may help reduce this even further but this should be determined by simulation and has to be a trade-off with other factors as in any design.


Advanced Design for SMT – Barry Olney, In-Circuit Design Pty LtdPCB Stack-up – Henry Ott ConsultantsICD Stackup Planner – In-Circuit Design Pty Ltd (download from )

Barry Olney is Managing Director of In-Circuit Design Pty Ltd. (ICD), Australia, a PCB Design Service Bureau and Board Level Simulation Specialist. ICD was awarded “Top 2005 Asian Distributor Marketing,” and “Top 2005 Worldwide Distributor Marketing” by Mentor Graphics, Board System Division. For more information, contact Barry Olney at +61 4123 14441 or email at

All consideration has been taken to ensure that this Application Note is accurate, based on the information and data available. The liability of In-Circuit Design Pty Ltd is limited to correcting any unforeseen errors and revising the Application Note to meet the specified requirements. In no event shall In-Circuit Design Pty Ltd be liable for indirect, special, incidental, punitive or consequential damages including but not limited to whether occasioned by the act, breach, omission, default or negligence of In-Circuit Design Pty Ltd, its employees, contractors and subcontractors, and shall include without limitation, loss of business, revenue or profits, loss of use or data, loss of savings or anticipated savings, loss of investments, loss of goodwill, loss of reputation or cost of capital or loss of extra administrative cost, or economic loss, whether or not foreseeable, and arising out of or in connection with this Application Note. All trademarks are registered trademarks of their respective owners. E&OE                       


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