HDPUG Demonstrates Benefits of Cooperative R&D
Feeling very privileged to be invited to attend the open presentations day of the annual European meeting of the High Density Packaging User Group (HDPUG), I travelled to Royal Leamington Spa in Warwickshire, UK, on May 27 with guest speaker Michael Weinhold, Technical Director of the European Institute of Printed Circuits (EIPC).
The High Density Packaging User Group (HDPUG) is a member-driven, non-profit, project-oriented industry consortium that addresses the integration of new electronics component packaging and interconnection technologies into the supply chains of its member companies. Its stated mission is to reduce the costs and risks for the electronics industries when utilising high-density electronic packaging, and it achieves its objective by promoting the concept of cooperative R&D – sharing scarce resources and expertise to address issues of common interest, to enable major problems and global technical issues to be resolved in a fraction of the time and at a fraction of the cost it would take for individual companies to do it alone.
HDPUG holds four two-day member meetings each year, two in the United States, one in Europe, and one in Asia. The first day is devoted to public-domain project presentations, with non-members attending by invitation, and members-only discussions take place on the second day.
HDPUG Executive Director Marshall Andrews opened this year's European meeting, welcomed members and guests, stated the ground rules: "We do not discuss IP and we do not discuss price," and introduced Martin Cotton, Director of OEM Marketing at Ventec, who had sponsored the event.
Cotton echoed Andrews' welcome and gave a brief history of the evolution of Ventec as a leading supplier of high-performance PCB substrates and its commitment to providing ultra-clean materials in thicknesses as low as 25 microns for HDI applications. Speaking from his many years' experience as a designer, he cautioned against over-specifying material and carrying the cost of performance overshoot. It was not uncommon for designers to specify the highest-performance – and consequently highest-cost – material for an application where its use was not technically justified, rather than put effort into the design exercise.
Cotton questioned whether designers really understood the significance of material properties other than electrical, and explained Ventec’s policy of rationalising their data sheets to clarify physical properties and actual constructions, and his personal role in working with OEM designers to help them to choose and specify the most appropriate and cost-effective solution.
HDPUG project facilitator John Davignon chaired the project-review session, which began with a Phase 2 status update on the Optical Interconnection project, presented by Marika Immonen from TTM in Finland, and Richard Pitwon from Seagate Technology in the UK. The project had begun five years previously with the objective of evaluating the feasibility and maturity of optical waveguide based technologies on PCBs, determining performance benefits and limitations using polymer waveguides and fibres for 1-2m links. The focus was on optical fibre and waveguide link characteristics, practical connectivity options and end-to-end link implementations. The project was now at Phase 2; Richard Pitwon described the test vehicle used as a complete system-level demonstrator platform, consisting of a backplane with pluggable daughter cards and mezzanine cards with 28Gbps connectors, for testing flexible and embedded waveguides. High speed 28Gbps test data could be driven across the platform from an external data source or from a pluggable logic card. The project team was currently working with Fraunhofer Institute to study glass waveguides, which had lower loss characteristics at longer wavelengths.
Through-silicon-via specialist Dave Love, HDPUG facilitator for TSV packaging, gave updates on the TSV Signal Integrity and TSV Board Level Reliability projects, in a context of current debate about the potential improvements in power and signal integrity to be gained by 2.5D packaging compared with traditional package-on-printed-circuit-board technology. The objective of the Signal Integrity project goal was to measure of differences. The project was at the definition phase: technical choices had been made on device-under-test and methods to compare signal launches for devices mounted on TSV interposer through the PCB to devices mounted on interposer on the same PCB with devices mounted in traditional packages through the PCB to devices mounted in traditional packages on the same PCB. The project was open to available samples and critical mass was needed to move it forward. The Board Level Reliability project recognised the lack of industry data on board-level reliability for 2.5D packaging, particularly in temperature cycling for high end computer and network applications, and drop and mechanical shock performance in mobile applications. Package suppliers typically focused on package-level qualifications, and 2.5D devices had weak structures susceptible to damage from strains imposed by being soldered to a PCB. The project presented the opportunity to quantify the risk by collaborative research and to publish the findings. A by-product would be characterisation of SMT assembly and the publication of a guideline document.
High speed press fit connectors with fragile, small-diameter pins on dense pitches and with tight tolerances, can be easily damaged during insertion and require rework. HDPUG facilitator Jack Fisher was joined by project leader Lars Bruno from Ericsson calling-in, to give an update on the Press Fit Rework project. The project objective was to determine and document the effect of rework on press fit connection strength, hole wall deformation and gas-tightness for new high-speed press fit connectors, using standard DIN connectors as a point of reference. The experimental plan was to perform a series of insertion and removal operations on a range of four high-speed back-plane connectors on two sets of eight PCBs, made on a standard base material, finished in either ENIG or immersion tin, with hole sizes at nominal, maximum tolerance and minimum tolerance, and study the results by microsectioning in horizontal and vertical axes. The biggest challenge anticipated was in achieving the critical hole diameters required for meaningful measurement in the light of normal drill-diameter and drilling machine process tolerances. The results were due to be published as a report in Q1 2016, indicating which pin and design combinations would best withstand rework, and what could be expected in terms of strength and hole wall deformation.
Love returned to report the progress of the X-Ray Tomography and Signal Integrity project, being carried out in collaboration with Professor Sven Simon of the University of Stuttgart. The project, which was now in definition phase, was seen as a useful adjunct to the award-winning High-Frequency Materials project. After completion of Df and Dk testing during the High Frequency Measurements Project, short-pulse-propagation samples, manufactured by two fabricators on multiple materials, had been sent to the University of Stuttgart, who proposed to use high-resolution X-ray tomography to generate manufacturing tolerance data, import the geometry data into 3D electrical models and output S-parameters for the test coupon circuits. The university had a new detector with 1.5 micron resolution, but had suffered some commissioning problems that had led to a delay. To have gone elsewhere at this stage in the project would have been prohibitively expensive, so the team was waiting on the equipment supplier to fix the problems. Once the project got under way, it could provide statistical data on tolerances and directly correlate tested Dk and Df values to actual geometries. The technique, if successful, would be very helpful to signal integrity engineers and would offer a non-destructive alternative to cross-sectioning.
Weinhold's guest presentation was entitled "Added Value PCBs in Europe", and focused on PCB design and production for embedded devices and the requirements for their successful introduction. His main message was: "We should only do what the industry needs, not what we personally need." Weinhold commented that added-value PCBs in Europe were more important every day, and the automotive industry expected a 15-year service life, whereas PCBs built to mobile phone standards were unlikely to last more than three years.
Global PCB production in 2012-2013 had been of the order of $60 billion, of which the United States accounted for 5%; Europe, 4.5%; and Asia, 90%. The United States and Europe continued to be the technology drivers, but for how long? Whatever business companies operated in—PCB design, PCB fabrication, component manufacturing, electronic device manufacturing or automotive manufacturing—the primary business objective was to make money! There was potential to make money through innovative new electronic products, with a focus on volume production, using competence and existing know-how, investing money and resources in future technologies, and targeting markets with growth opportunities.
Weinhold examined the meaning of "reliability" in a present-day context. In the past, reliability had been measured as mean-time-between-failures. Now, it was mean-time-to-failure. In other words, equipment should not fail at all. And if it did, repair was generally not possible.
So, having established two themes: innovation and reliability, Weinhold asked the question: "How can embedded components add value?" He reviewed the evolution of embedded component technology from the ceramic hybrids of the 1960s to the technologies of the present, based on organic printed circuits. Ceramics were more suited to harsh environments, but were expensive. PCB-based solutions, although technically inferior, were more cost-effective although certain developments like SIMOVE had been obsoleted by developments in silicon technology. But the design cycle for silicon was much longer than, for example, designs based on low-temperature co-fired ceramic, so for small volumes ceramic offered a viable solution.
In general, fixed costs for silicon were enormously higher than those for PCB or LTCC, but variable costs were much lower, and design-on-silicon was an enabling technology for cost reduction. Compromises between cost reduction and innovation were key drivers for the PCB fabricators and OEM and EMS companies in Europe. Device embedding technology in Europe was used to add electronic, mechanical, thermal management and environmental function to PCBs. For PCB fabricators, embedding was a step towards integration in the supply chain, and would shift the focus away from the PCB assembler to the bare board PCB fabricator. Designers would have to understand that testing would have to be carried out at the inner-layer sub-assembly stage.
Discussing industrialisation targets, Weinhold referred to the EU-funded HERMES project, which had resulted in successful product development, with the benefits of PCB technology modified to be a fully-functional means of cost-effective chip packaging, and the chip-in-polymer process had been an industrialised outcome. In automotive electronics, the biggest growth area was anti-collision radar, and KRAFAS was a cost-optimised sensor for 77GHz active driver assistance system which had been an outcome of another funded project. Now that new design software capability was available, embedding components in PCBs had great potential to enable innovative mechatronic solutions.
The afternoon session began with Stephanie Moran of Oracle reporting progress in the Smooth Copper Signal Integrity project, in its definition phase and proceeding into implementation. "We spend a lot of money on smooth copper foil, and then roughen it up for bonding," she noted. Signal integrity as measured by insertion loss was a critical consideration at higher frequency, and the surface roughness of copper foil was a major factor. It had been observed that inner-layer bonding treatments could contribute up to a 50% change in loss performance. The project objective was to evaluate the effects of adhesion promoters when applied to initially smooth copper, to electrically measure the insertion loss of commonly used cleaning and adhesion-promoting treatments, and to measure the copper surface roughness before and after each treatment. A six-layer test vehicle was being designed, with four ground layers and two internal signal layers, built on Megtron 6 with ½oz HLVP copper. The chemical bonding treatment would be the only variable. The test vehicle would have coupons for signal integrity measurement in the 1-20GHz range and thermal shock testing. Copper surface roughness would be measured by white light interferometry and laser scanning confocal microscope techniques. Six proprietary adhesion promotors had been selected for evaluation. The results would lead to a better understanding of best and worst case scenarios for modelling purposes and increase awareness of poor treatment choices for smooth copper in high speed applications.
HDPUG facilitator Larry Marcanti introduced Phase 2 of the Printed Wiring Board Environmental Life Cycle Analysis project, and was joined by project leader Erkko Helminen from TTM Technologies calling-in. The project recognised that for many consumer electronic products, the greenhouse gas emissions associated with production had a significant impact on the overall lifetime emissions of the product and there was a clear and urgent need for a greenhouse gas analysis tool for PWB fabrication which would take into account design and construction details, how and where the PWBs were made and how efficient the process was.
Phase 1 of the project had resulted in an Excel-based tool to calculate the amount of greenhouse gas emissions and water usage associated with the fabrication of PWBs, based on actual energy and water consumption data from a volume manufacturing facility. The tool differentiated between various designs and constructions, and factored-in the impact of different power generation techniques across different geographical regions. It also included emissions associated with production of process chemicals and raw materials.
Phase 2 of the project aimed to develop a more flexible and more representative calculation tool with enhanced accuracy and reduced uncertainty, with additional capability to support emerging PWB technologies, and compatibility with any fabrication facility. There was a need to raise industry awareness of the project and engage with additional participants to develop ongoing tool maintenance and upgrade strategies.
Neil Chamberlain from Polar Instruments described the objectives of the High Frequency Flex Project, originally proposed at the HDPUG autumn meeting in Canada and now in the idea phase. The aim was to characterise the effects of design features, material choices and operating environments on signal integrity for flexible and flexi-rigid printed circuit boards operating at high-end digital transmission frequencies. The project specifics had yet to be defined but would likely involve the design, fabrication and electrical performance analysis of FPC test vehicles. An idea-phase team had been formed and initial discussions on four areas of concern had been completed. The current objective of the team was to build a test vehicle to evaluate how different cross-hatch designs affect impedance and insertion and return loss parameters, and the project would shortly move into definition phase. It was still open to new participants and was presently seeking project resources.
Fisher presented an update on the Future HDI project on behalf of Ivan Straznicky from Curtiss-Wright. The project was at the definition stage and recognised that BGA pitch continued moving steadily towards 0.5mm and 0.4mm. Consumer electronics were using any-layer-via HDI PCBs to support very fine pitch BGAs with large arrays. Although these were typically too thin for telecom/server and aerospace/defence applications, data transmission speeds were trending towards the 100GHz level, and back-drilling of through-hole vias was becoming common. A test vehicle had been designed featuring two any-layer outer sub-stack constructions with sintered copper paste vias, built over a conventional multilayer core with offset vias. Layers 1/2 and n/n-1 were plated copper, not sintered paste, and the overall construction had plated-through holes for press-fit connectors. The production sequence would involve a maximum of four laminations and two plating steps.
This test vehicle would serve as a development platform for PCB fabricators, and enable the determination of the current carrying capability of stacked sintered copper-paste vias, their lead-free survivability and IST thermal cycle reliability, and also their susceptibility to CAF. It would also allow thermal ageing and CTE mismatch effects to be studied, and electrical performance related to material stability. The test vehicle would be manufactured by multiple fabricators – six had already signed up – each choosing their own preferred methods and materials, in a 24" x 18" panel size with coupons for IST and delamination, current carrying capability, CAF, high-strain part-assembly daisy chain, accelerated thermal cycling and impedance. The design team was at the stage of finalising the details of the test vehicle, continuing the resource definition and commitment, and creating the project plan. The design was scheduled to be ready for fabricator review by end of June 2015, with fabrication completed by end of November and samples ready for testing mid-December.
Oracle's Moran returned to present the update of Phase 2 of the High Frequency Test Methods project on behalf of Karl Sauter from Oracle. It was known that some high frequency test methods, in the frequency range of 1GHz to 20GHz, measured significantly different Dk and especially Df values depending upon the moisture content of the laminate material being tested. Phase 1 of the project showed strong Dk and Df data correlations between high frequency test methods that were of the same type. However, differences in moisture content were found to contribute up to a 20 percent difference in the measured Df values of certain laminates.
Phase 2 proposed to evaluate the effect of moisture on each of the laminate material high frequency Dk and Df test methods, with the exception of equivalent bandwidth. The lower-loss laminate materials selected for testing would be those known to absorb significant amounts of moisture, but without any fillers capable of releasing moisture into the resin system during thermal excursions or at higher temperatures. Measurement of the dielectric parameters presented no problems, and the same techniques would be used as in Phase 1. The biggest challenge was the accurate measurement of small weight changes with a microbalance.
Marcanti returned to present the Harsh Use Environment Alloy Evaluation project, presently at the idea stage. The project proposed to evaluate lead free solders to determine their suitability for harsher environmental and use conditions such as transportation, and defence applications, where the requirement could not be met with SAC alloys. Several calls had been made to discuss the proposal, and there was potential to collaborate with iNEMI and AREA consortium. The team had developed an interest matrix to define of the scope of the work, a series of solder alloys had been identified and several tools and test vehicles were already available for the evaluation. It remained to finalise the alloy list, testing protocol and commitments for test profiles and testing resources, and to draft the project plan in readiness for seeking board approval to proceed to implementation.
Denny Fritz from SAIC called-in to report on the Counterfeit PCB Materials project. The initial working group had identified two threats: safety, for example where an electrical fire resulted from the failure of a counterfeit solder mask, and trust, where the whole board was counterfeit, or where circuitry was added to design to accommodate malicious third party intent. It had been agreed to limit the scope of the project to the safety aspect in the first instance, and the primary objective was to identify and investigate safety as a function of counterfeit materials in the electronics industry and to produce a white paper assessing the validity of claims concerning potential insecure practices in the PCB Materials industry, dispelling or validating known rumours and recommending any changes needed. These recommendations might include possible surveillance schemes or techniques and third party verification of the chemical composition of materials.
HDPUG project facilitator Bob Smith reviewed Phase 2 of the FCBGA Package Warpage project, which was at definition stage. The goal was to establish a limit for dynamic package warpage that could be mitigated during board assembly without impacting solder joint quality. Phase 1 of the project had been to develop a test method to enable the team to compare and contrast the effects of the mitigation techniques.
The objective of Phase 2 was to establish the maximum warp an optimised process could accommodate and characterise the contribution of the mitigation techniques on the process yield. A modified hot air rework station was used to simulate the dynamic warpage characteristics of the FCBGA package, by lifting the component up or down at different temperatures. A video camera monitored the solder joints on the outside row on one side of the package. The material parameters being studied were solder paste activity, solder paste tackiness, solder paste volume, reflow profile, peak temperature, reflow atmosphere and cooling rate. Test vehicle samples were in the process of being assembled, and testing was scheduled to commence in July 2015.
At the end of each presentation, a sign-up sheet was circulated to enable members to indicate their interest in joining that project.
In the final session of a full and varied day, Fisher moderated a review of the follow-up status of ideas for new project proposals: Richard Coyle from Alcatel-Lucent, on a call-in, detailed the proposals for both the SAC Ageing 3 project and the Industry Consortia Collaboration and Resource Management for Thermal Fatigue Evaluations of Alternate Lead-free Alloys project. Other ideas described were Board Thickness Impact on Component Accelerated Thermal Cycling Performance and Effect of Rework on Component reliability.
Fisher commented that there were effectively four levels of technology: industry level, enterprise level, corporate level and operational level; and HDPUG’s sweet spot was in the operational and corporate area, where members could collaborate and cooperate in seeking non-competitive industry solutions. HDPUG's projects continued to provide substantial savings and resource leveraging for its members by sharing the costs of research, raising the awareness of the industry and encouraging material suppliers to develop materials to address its issues and manufacturing companies to adopt procedures and techniques of mutual interest.
It was an eye-opening and technically stimulating day for an outsider. What impressed me most was the feeling of community spirit and the willingness of members to share skills and resources. Many thanks, HDPUG, for giving me the opportunity to understand a little about how your organisation operates.