Reading time ( words)
The quad data rate IV (QDR-IV) memory interface protocol is used for reduced-latency applications. It features two independent bi-directional data channels, each running at double data rate (DDR).
Mentor Graphics’ newest white paper walks PCB designers through several ways to capitalize on the benefits of the DDRx Wizard batch simulation to validate the QDR-IV bus. This PDF is available for download by clicking here.
Chang Fei Yee, Keysight Technologies
This article briefly introduces the 4-level pulse amplitude modulation (PAM-4) and its application in 400 Gigabit Ethernet (400GbE), to support the booming data traffic volume in conjunction with the deployment of 5G mobile communications. Furthermore, this article also highlights the essential pre-layout effort from signal integrity perspective for physical (PHY) link design on a PCB, including material selection, transmission line design and channel simulation to support 56Gbps data rate that paves the way for seamless communication in 400GbE.
I-Connect007's Happy Holden reviewed the recently concluded IPC APEX EXPO 2018. Among the highlights: Less than 10% of all new orders arrive at the PCB fabricator’s facility with complete, accurate design data. Most have missing or incorrect data.
I-Connect007 Editorial Team
During the Design Forum at IPC APEX EXPO 2018, Jan Pedersen, senior technical advisor for the PCB broker Elmatica, gave a presentation on CircuitData. The language is designed to help facilitate other design data transfer formats such as Gerber, ODB++, and IPC-2581. Jan spoke with Managing Editor Andy Shaughnessy and Contributing Technical Editor Happy Holden about how this open language works with the existing data formats, as well as the need to eliminate paper documents from design process, and how the industry can help shape this open-source language.