Reading time ( words)
We’re sad to report late-breaking news that independent engineering consultant Steve Weir has died. No details are available at this time.
Steve was a power and signal integrity guru with a variety of patents to his name. A fixture of DesignCon and a constant presence on the SI-List signal integrity forum, Steve wrote over a dozen papers on power integrity.
He also had a crazy, irreverent sense of humor that you don’t find among most engineers. I first met Steve about 10 years ago at DesignCon. He introduced me to a few other EEs, with caveats such as, “John’s an SI engineer, but more importantly, the statute of limitations has run out on his unprosecuted felonies. And don’t let him near your wife. Or your son, for that matter.”
It was like that with Steve. He didn’t seem to have a pause button. The world needs more people like that.
He will be missed.
Yuriy Shlepnev, Simberian
The usual way of signaling through PCB interconnects is a two-level pulse, an encoding of 1s and 0s or bits, named NRZ (non-return-to-zero) or PAM-2 line code type. Increasing the data rate with the NRZ code type presents some obstacles. For a 28 Gbps NRZ signal, the bit time is about 35.7 ps with the main spectral lobe below 28 GHz. For a 56 Gbps NRZ signal, the bit time is about 17. 86 ps, with the main spectral lobe below 56 GHz. One can feel the problem already: Getting PCB interconnect analysis and measurements up to 56 GHz and beyond is very challenging, to say the least.
Bill Acito, Cadence Design Systems
The challenges faced by the PCB designers of today are significant. If we examine the breadth of designs, we find ever-increasing data rates and more high-speed signal routing that drive additional challenges meeting signal-quality requirements, including reflection signal loss and crosstalk issues. At the same time, designers are being asked to complete designs in shorter cycle times and in smaller form factors. They must come up with new and more complex routing strategies to better control impedance and crosstalk. Manual implementation is often time-consuming and prone to layout errors.
Christian Keller, Altium
PCB developers are deluged with new challenges caused by increasing density and smaller components. Ball grid arrays (BGAs) create particular challenges during layout, with hundreds of connections in just a few square centimeters. Fortunately, designers now have options for addressing these issues.