Failure Mode: Hole Wall Pullaway


Reading time ( words)

Hole wall pullaway (HWPA) is an insidious defect that is not usually a cause of electrical failure. What happens with HWPA is that the copper plating in a plated through-hole (PTH) is pulled away from the dielectric of the drilled hole wall. The hole must not be filled with any sort of a hole fill in order to see HWPA.

There are two distinct types of HWPA: stress-relieving and stress-inducing. In stress-relieving HWPA, the condition appears to distress the PTH, allowing it to survive hundreds or thousands of thermal cycles without failure. In stress-inducing HWPA, the stress appears to greatly increase, causing the PTH to fail in just a few thermal cycles. What we consider a failure is an increase greater than 10% in the overall resistance in the circuit. A crack that partially bridges the copper at the internal interface is enough to cause a failure.

This column is based on my experience in test reliability of interconnect stress test (IST) coupons. I am addressing HWPA that features moderate to severe outgassing. There may be HWPA due to thermal stressing of the board without any significant outgassing, but this type of HWPA is subtle, and it presents as a dark line between the plating and the dielectric of the hole wall. This type of HWPA is rarely detected.

Stress-Relieving HWPA

Stress-relieving is the most common type of HWPA. It appears that the adhesion of copper plating to the dielectric is reduced most likely due to problems with the application of electroless copper plating adhering to the dielectric of the hole wall. At the same time, the adhesion is strong at the copper’s internal interconnection. In fact, experience suggests that the adhesion of the electroless copper is stronger than the copper plating. This process frequently produces strong interconnections to copper inner layers. This condition may result in a hole wall that looks like a stack of forward or backward “Ds” running the length of the hole where the top and the bottom of the “Ds” is at an internal interconnect.

To read this entire article, which appeared in the August 2015 issue of The PCB Design Magazine, click here

Share




Suggested Items

Optimizing Communication Between Fabricators and Designers

03/21/2023 | Andy Shaughnessy, Design007 Magazine
During DesignCon, I spoke with James Hofer from Accurate Circuit Engineering about some of his customers' biggest challenges. We discussed various ways to increase the level—and quality—of communication between designers and fabricators. James also offered some interesting observations about bridging the gap between designer and fabricator. How often do you communicate with your fabricator?

DFM 101: Final Finishes: OSP

03/09/2023 | Anaya Vardya, American Standard Circuits
One of the biggest challenges facing PCB designers is not understanding the cost drivers in the PCB manufacturing process. The next final finishes to discuss in this series is OSP. As with all surface finishes there are pros and cons with the decision of which to use. It is a combination of application, cost, and the properties of the finish. OSP is RoHS-compliant as there is zero lead content in the finish.

DFM 101: Final Finishes—HASL

02/14/2023 | Anaya Vardya, American Standard Circuits
One of the biggest challenges facing PCB designers is not understanding the cost drivers in the PCB manufacturing process. This article is the latest in a series that will discuss these cost drivers (from the PCB manufacturer's perspective) and the design decisions that will impact product reliability.



Copyright © 2023 I-Connect007 | IPC Publishing Group Inc. All rights reserved.