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Optimizing large pin-count FPGAs is challenging. Manual optimization can take days and result in reduced quality.
This new video from Mentor Graphics shows how signal pin assignments can be automatically optimized between multiple FPGAs on the PCB while respecting pin-specific rules and constraints. Reduce the number of routing layers, minimize crossovers and overall trace lengths on the PCB, and reduce signal integrity issues for higher completion rates and shorter FPGA route times.
To watch this video, click here.
Yuriy Shlepnev, Simberian
A typical PCB design usually starts with the material selection and stackup definition—the stackup planning or design exploration stage. How reliable are the data provided by the material vendors and PCB manufacturers? Can we use these data to predict trace width and spacing for the target trace impedance or to calculate delays or evaluate the loss budget?
Chang Fei Yee, Keysight Technologies
In electronic systems, signal transmission exists in a closed-loop form. The forward current propagates from transmitter to receiver through the signal trace. Meanwhile, the return current travels backward from receiver to transmitter through the power or ground plane directly underneath the signal trace that serves as the reference or return path. The path of forward current and return current forms a loop inductance. It is important to route the high-speed signal on a continuous reference plane so that the return current can propagate on the desired path beneath the signal trace.
Andy Shaughnessy, PCBDesign007
I had the opportunity to talk with our contributor Doug Brooks recently. He has been doing some research on temperature effects on PCB traces over the last few years, and I wanted to check the status of his latest thermal efforts. He discussed his work with Dr. Johannes Adam, why temperature charts based on a trace in isolation are inaccurate, and how the industry remained so wrong about PCB temperatures for so long.