Mentor Graphics Video: Automatically Unravel Complex FPGA Signals


Reading time ( words)

Optimizing large pin-count FPGAs is challenging. Manual optimization can take days and result in reduced quality.

This new video from Mentor Graphics shows how signal pin assignments can be automatically optimized between multiple FPGAs on the PCB while respecting pin-specific rules and constraints. Reduce the number of routing layers, minimize crossovers and overall trace lengths on the PCB, and reduce signal integrity issues for higher completion rates and shorter FPGA route times.

To watch this video, click here.

Share

Print


Suggested Items

Words of Advice: What Feature Would You Like to See in Your CAD Tool?

10/31/2019 | Andy Shaughnessy, Design007 Magazine
In a recent survey, we asked the following question: What feature would you like to see in your CAD tool? Here are a few of the answers, edited slightly for clarity.

Words of Advice: What Feature Would You Like to See in Your CAD Tool?

09/16/2019 | I-Connect007 Research Team
In a recent survey, we asked the following question: What feature would you like to see in your CAD tool? Here are a few of the answers, edited slightly for clarity.

Decoupling Capacitors’ Impact on Power and Signal Integrity

09/03/2019 | Chang Fei Yee, Keysight Technologies
It is crucial for hardware designers to identify the resonant frequency of each element of the PDN on a PCB and its impact on power integrity. A PCB with poor power integrity—such as a higher-than-targeted PDN impedance across the wideband range—results in SSN and a shrunken eye diagram of the signal transmitted by the IC that draws power from the PDN. This article demonstrates the post-layout co-simulation of power and signal integrity.



Copyright © 2019 I-Connect007. All rights reserved.