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Mentor Graphics Video: Automatically Unravel Complex FPGA Signals
December 2, 2015 | Mentor GraphicsEstimated reading time: Less than a minute
Optimizing large pin-count FPGAs is challenging. Manual optimization can take days and result in reduced quality.
This new video from Mentor Graphics shows how signal pin assignments can be automatically optimized between multiple FPGAs on the PCB while respecting pin-specific rules and constraints. Reduce the number of routing layers, minimize crossovers and overall trace lengths on the PCB, and reduce signal integrity issues for higher completion rates and shorter FPGA route times.
To watch this video, click here.
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The Pulse: Drilling Down on Documentation
04/18/2024 | Martyn Gaudion -- Column: The PulseHow did a product aimed at signal integrity end up being more about documentation? For a little backstory, the Polar team has an unspoken “no business speak” rule at certain times. So, why is this column titled “Drilling Down?” I find it fascinating when a company sets off in one direction, but customers steer it in another. That’s what has happened here as customers took a product down a fork in the road we couldn’t predict. Your destination isn’t always where you initially set off to go, and that’s how we got to our subject of drills and drill documentation.
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Embedded World 2024: Rohde & Schwarz Presents its Cutting-edge Test Solutions for Embedded Systems
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Reassessing Surface Finish Performance for Next-gen Technology, Part 2
03/04/2024 | Frank Xu, PhD and Martin Bunce of MacDermid Alpha, and John Coonrod of Rogers Corp.The introduction of 5G/6G has created a growing demand for faster rates of data transfer and operation at higher frequencies, pushing signals to travel toward the outer edges of conductors. As a result, the surface finish applied over the copper circuitry is now gaining more attention.