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Optimizing large pin-count FPGAs is challenging. Manual optimization can take days and result in reduced quality.
This new video from Mentor Graphics shows how signal pin assignments can be automatically optimized between multiple FPGAs on the PCB while respecting pin-specific rules and constraints. Reduce the number of routing layers, minimize crossovers and overall trace lengths on the PCB, and reduce signal integrity issues for higher completion rates and shorter FPGA route times.
To watch this video, click here.
Andy Shaughnessy, Design007 Magazine
At DesignCon 2018, I ran into Mentor’s Fadi Deek, the author of both of Mentor’s I-Connect007 eBooks: the newest, "The Printed Circuit Designer’s Guide to Power Integrity by Example," and their first book, "The Printed Circuit Designer’s Guide to Signal Integrity by Example." We sat down and discussed how the idea for the books came about, as well as some of the power integrity challenges facing PCB designers and engineers.
Kelly Dack, CID+, EPTAC
DesignCon is always a great place to check out the latest PCB layout and simulation software tools. During DesignCon 2018, Guest Editor Kelly Dack met with Sam Chitwood, a product engineer with Cadence. Sam explained how the Cadence Sigrity simulation software now allows users to make decisions early in the design process, and how this can help optimize the design of the power delivery network and ensure signal integrity in complex PCBs.
Successful signal integrity analysis depends on a fundamental concept: impedance. Without a thorough understanding of the impedance values that a signal encounters along the way, designers cannot maintain good signal quality from source to receiver.