Reading time ( words)
A high-speed digital power distribution network (PDN) must provide a low inductance, low impedance path between all ICs on the PCB that need to communicate. In order to reduce the inductance, we must also minimize the loop area enclosed by the current flow. Obviously, the most practical way to achieve this is to use power and ground planes in a multilayer stackup. In this two-part column, I will look at the alternatives to planes, why planes are used for high-speed design, and the best combination for your application.
Back in the mid-eighties, when I worked at the University of Western Australia, one of my duties was to fix the departmental mainframe: the dreaded DEC PDP-11/40. When it broke down, it was a two-week sentence to solitary confinement in the frigid computer room. This monster machine had card after card with rows of TTL logic chips. Figure 1 illustrates a typical Unibus board. It had 8K, 16-bit word core memory, which I believe could be expanded to 80K if the need ever arose. The core had a 400ns access time, which means the system clock would have been a blazing 2.5MHz.
I always used the “divide and conquer” methodology. First, eliminate the power supplies then start dividing the system in half, then half again until the fault was localized within a small circuit. But, as it took about half an hour to reboot, with a specific sequence of octal latches, it was a very time consuming process. Plus, there were always numerous engineering students banging on the window, to the terminal room, enquiring when the “mother” might be fixed so they could complete their assignments.
The boards were double-sided and used a power finger, type A or B layout configuration on the top side of the board, as shown in Figure 2. The bottom side could then be used entirely for routing. This provided some mutual inductive coupling between the wide power and ground traces and saved on board area. However, it meant that the return current had to flow all the way around the board perimeter, creating a large loop area. Fortunately, the PDP-11/40 was manufactured way before the era of FCC-mandated radiation guidelines. Needless to say, this is not a good supply configuration for high-speed design. Don’t try this at home!
To read this entire article, which appeared in the December 2015 issue of The PCB Design Magazine, click here.