Beyond Design: Plane Crazy, Part 1


Reading time ( words)

A high-speed digital power distribution network (PDN) must provide a low inductance, low impedance path between all ICs on the PCB that need to communicate. In order to reduce the inductance, we must also minimize the loop area enclosed by the current flow. Obviously, the most practical way to achieve this is to use power and ground planes in a multilayer stackup. In this two-part column, I will look at the alternatives to planes, why planes are used for high-speed design, and the best combination for your application.

Back in the mid-eighties, when I worked at the University of Western Australia, one of my duties was to fix the departmental mainframe: the dreaded DEC PDP-11/40. When it broke down, it was a two-week sentence to solitary confinement in the frigid computer room. This monster machine had card after card with rows of TTL logic chips. Figure 1 illustrates a typical Unibus board. It had 8K, 16-bit word core memory, which I believe could be expanded to 80K if the need ever arose. The core had a 400ns access time, which means the system clock would have been a blazing 2.5MHz.

I always used the “divide and conquer” methodology. First, eliminate the power supplies then start dividing the system in half, then half again until the fault was localized within a small circuit. But, as it took about half an hour to reboot, with a specific sequence of octal latches, it was a very time consuming process. Plus, there were always numerous engineering students banging on the window, to the terminal room, enquiring when the “mother” might be fixed so they could complete their assignments.

The boards were double-sided and used a power finger, type A or B layout configuration on the top side of the board, as shown in Figure 2. The bottom side could then be used entirely for routing. This provided some mutual inductive coupling between the wide power and ground traces and saved on board area. However, it meant that the return current had to flow all the way around the board perimeter, creating a large loop area. Fortunately, the PDP-11/40 was manufactured way before the era of FCC-mandated radiation guidelines. Needless to say, this is not a good supply configuration for high-speed design. Don’t try this at home!

To read this entire article, which appeared in the December 2015 issue of The PCB Design Magazine, click here.

Share


Suggested Items

3D Convergence of Multiboard PCB and IC Packaging Design

07/18/2018 | Bob Potock, Zuken
A new generation of 3D multiboard product-level design tools offer major improvements by managing multiboard placement in both 2D and 3D, and enabling co-design of the chip, package and board in a single environment. Multiboard design makes it possible to create and validate a design with any combination of system-on-chips (SOCs), packages, and PCBs as a complete system. Chip-package-board co-design enables designers to optimize routability via pin assignment and I/O placement to minimize layer counts between the package, chip and board. The new design methodology makes it possible to deliver more functional, higher performing and less expensive products to market in less time.

Dave Wiens Discusses Multi-board Design Techniques

07/09/2018 | Andy Shaughnessy, I-Connect007
For our multi-board design issue, I interviewed Dave Wiens, product marketing manager for Mentor, a Siemens business. We discussed how the multi-board design technique differs from laying out single boards, along with the planning, simulation and analysis processes required to design multi-board systems.

Paving the Way for 400Gb Ethernet and 5G

06/26/2018 | Chang Fei Yee, Keysight Technologies
This article briefly introduces the 4-level pulse amplitude modulation (PAM-4) and its application in 400 Gigabit Ethernet (400GbE), to support the booming data traffic volume in conjunction with the deployment of 5G mobile communications. Furthermore, this article also highlights the essential pre-layout effort from signal integrity perspective for physical (PHY) link design on a PCB, including material selection, transmission line design and channel simulation to support 56Gbps data rate that paves the way for seamless communication in 400GbE.



Copyright © 2018 I-Connect007. All rights reserved.