Beyond Design: Plane Crazy, Part 2


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In my recent four-part series on stackup planning, I described the best configurations for various stackup requirements. But I did not have the opportunity to delve into the use of planar capacitance to reduce AC impedance at frequencies above 1GHz, which is the region wherein bypass and decoupling capacitors dramatically lose their impact. In this column, I will flesh out this topic, and consider the effects of plane resonance on the power distribution network (PDN).  

Figure 1 illustrates a 12-layer DDR3 board with six routing layers and six plane layers utilizing multiple technologies. This board must accommodate 40/80-ohm single-ended/differential impedance for DDR3, 90-ohm differential USB, and the standard 50/100-ohm digital impedances all on the same substrate. In order to reduce the layer count, it is important that these different technologies share the same layers. Plus, one needs to manage the return current paths and broadside coupling of the stripline configurations—quite a challenge!

The DDR3 matched delay signals are routed on the internal layers 3 & 4 and 9 & 10, which all use ground (GND) as the reference plane. To eliminate broadside coupling, the data lanes (eight in this case), differential strobes, and masks are routed on layers 3 & 4. And the adjacent traces are routed skewed or orthogonally. The address, control and command signals are routed together with the differential clock on layers 9 & 10. This separates the data lanes and address signals. Since DDR technology utilizes synchronous buses, the signals within the data lanes and within the address bus can be routed closely together, but the eight data lanes should be separated to avoid crosstalk.

As you can see, there are four planes in the center of the board, two power and two ground. This is where tight coupling, between adjacent planes, can be utilized to add planar capacitance at low cost and dramatically reduce the AC impedance at the high end. There are thin sheets of Isola 370HR 1080 prepreg (2.8 mils thick) between both planes pairs.

Given the effects of the capacitors equivalent series inductance (ESL) and mounting inductance, the added planar capacitance still reduces the overall impedance to approximately the target impedance up to 1GHz as in Figure 2. Now, this is not easy to do using standard stackups.

To read this entire article, which appeared in the January 2015 issue of The PCB Design Magazine, click here.

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