-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLevel Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
ICD Adds Matched Delay Optimization to Stackup Planner
June 20, 2016 | ICDEstimated reading time: 1 minute
In-Circuit Design Pty Ltd (ICD), Australia, developer of the ICD Stackup and PDN Planner software, has released a Matched Delay Optimization feature for the Stackup Planner.
Signals propagate at the speed-of-light in free space. However, this speed varies dramatically depending on the surrounding dielectric materials. Each layer, of a multilayer PCB, can have a very different propagation speed. This is particularly important for the latest high-speed DDR3/4 memory devices. The new “Matched Delay Optimization” feature, of the ICD Stackup Planner, allows you to not only match the length of busses, but takes this one step further by automatically calculating the appropriate length required to match the delay exactly. The integrated field solver simulates the flight time, of each signal layer, to quickly give you the results you need to effectively route memory.
“A matched length of 2.3 inches for a DDR3/4 Data lane can produce up to 70ps delta, between signal layers, leaving the timing way outside the required DDR3/4 setup and hold times,” said Barry Olney, CEO. “Designers need to pay strict attention to the signal propagation, on each layer, ensuring the total flight time of the critical signals match, regardless of length. The ICD Stackup Planner now allows you to optimize this delay."
The relative signal propagation is displayed as a bar graph, once the matched length has been set. Selecting “Matched Delay” automatically optimizes the length, of each signal layer, to match the maximum delay. The user can then route the data lane, to the exact delay, in their preferred design tool.
About In-Circuit Design Pty Ltd
In-Circuit Design Pty Ltd, based in Australia, developer of the ICD Stackup and PDN Planner software, is a PCB Design Service Bureau and specialist in board level simulation. Visit www.icd.com.au.
Suggested Items
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.