Perhaps you recently saw that Intel was awarded a contract for a SHIP by the U.S. Department of Defense. However, this one will not float on the water since SHIP stands for state-of-the-art heterogeneous integration prototype. Since that is a mouthful, let’s get a definition of heterogeneous integration :
“Heterogeneous integration (HI) refers to the assembly and packaging of multiple separately manufactured components onto a single chip to improve functionality and enhance operating characteristics. Heterogeneous integration allows for the packaging of components of different functionalities, different process technologies, and sometimes separate manufacturers. The combined devices can vary in functionality (e.g., processors, signal processors, cache, sensors, photonics, RF, and MEMS) and technologies (e.g., one optimized for die size with another one optimized for low power).”
I had mentioned the acronym SHIP in one of my previous columns titled “PCB-related OTAs From NAVSEA Crane,” published on October 29, 2019, just as SHIP Phase 1 was awarded. That work has been completed, and Phase 2 of the planned four phases has now been awarded. Also, the SHIP program contains two emphases: digital and RF. The digital portion will be led forward by Intel Federal with help from Xilinix, and the RF portion by Qorvo (Texas), Northrop Grumman, Keysight, and General Electric as partners. All were participants in the Phase 1 award. While Phase 1 was estimated at roughly $25 million, Phase 2 is reportedly for $172.7 million .
While the first phase was mostly planning and feasibility, the second phase will have at least one part of considerable interest to the PCB community—to develop prototypes of multichip packages. Besides making actual devices, Phase 2 will advance interface standards, protocols, and of utmost importance, concentrate on the security for heterogeneous systems .
The SHIP project is working hand-in-glove with the DARPA CHIPS effort focused on chiplets. In fact, frequent defense updates talk about the DARPA CHIPS effort and this SHIP program at the same time. SHIP prototypes will use some of the highly secure DoD “dielets” or chips and marry those to Intel’s advanced, commercially available silicon products, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and central processor units (CPUs). The hope is that this combination of some secure dielets with proven commercial known-good-die (KGDs) will make up for the loss of huge specialized defense ICs from sources such as IBM Fishkill (sold to Global Foundries over five years ago).
Of special interest to the printed circuit community is the near-PCB technology of Intel’s heterogeneous packaging technologies, including embedded multi-die interconnect bridge (EMIB), 3D Foveros, and Co-EMIB (combining both EMIB and Foveros) . These interconnection technologies are coming from Intel facilities in Oregon and Arizona.
Lest you think there is no rhyme nor reason behind these defense semiconductor efforts, the SHIP effort was mentioned in work sessions following the August 2020 Electronics Resurgence Initiative (ERI) from DARPA . Both Ellen Lord, undersecretary of defense for acquisition and sustainment, and Nicole Petta, principal director of the DoD’s Microelectronics Office, gave overviews of the both DARPA CHIPS and related activities like SHIP. I enjoyed watching the virtual presentations since I knew what I was listening for. (You may recall my January 2019 column on the DARPA ERI.)
As a further incentive, both House and Senate have 2020 proposals to secure even more funds for semiconductors and interconnection systems. As most readers of this column relate more to PCBs, I will only point out that the Creating Helpful Incentives to Produce Semiconductors (CHIPS) for America Act, in the U.S. Senate would allocate $5 billion to establish an Advanced Packaging National Manufacturing Institute under the Department of Commerce to establish U.S. leadership in advanced microelectronic packaging and, in coordination with the private sector, promote standards development, foster private-public partnerships, create R&D programs to advance technology, create an investment fund ($500M) to support domestic advanced microelectronic packaging ecosystem, and work with the Secretary of Labor on establishing workforce training programs and apprenticeships in advanced microelectronic packaging capabilities .
I know, another defense acronym using chips. Can you imagine an appropriation of $500 million when the combined value of all PCBs produced in the U.S. each year now is only $3–4 billion? Don’t spend those development dollars yet, as the U.S. defense budget (NDAA) has still not passed Congress, and the DoD is operating on a continuing resolution. Consider all this additional expenditure on semiconductor and interconnection technology, in light of the election results and the almost sure COVID-19 stimulus package, which should each have an impact on the hopeful electronics interconnection appropriation.
The SHIP Project with Navy Crane, Intel, and others should pave the way for the rapid integration of these future Congressional appropriations into a modernized defense supply chain for secure, world-class electronics.
- WikiChip, “Heterogeneous Integration (HI).”
- United Press International, “Pentagon awards $197M to Microsoft, Intel, others for microelectronics,” Gephardt Daily, October 16, 2020.
- David Manners, “U.S. DoD gives Intel packaging contract,” Electronics Weekly, October 5, 2020.
- Intel, “Up Close With Lakefield: Intel’s Chip with Award-Winning Foveros 3D Tech,” February 11, 2020.
- George Leopold, “DARPA Chip Effort Pivots to Securing U.S. Supply Chain,” Enterprise AI, August 20, 2020.
- Mark R. Warner, “Bipartisan, Bicameral Bill Will Help Bring production of Semiconductors, Critical to National Security, Back to U.S.” July 10, 2020.
Editor’s note: For more information on roadmaps, including the Heterogeneous Integration Roadmap (HIR), check out the October issues of SMT007 Magazine, Design007 Magazine, and PCB007 Magazine.
Dennis Fritz was a 20-year direct employee of MacDermid Inc. and is retired after 12 years as a senior engineer at (SAIC) supporting the Naval Surface Warfare Center in Crane, Indiana. He was elected to the IPC Hall of Fame in 2012.