One does not have to look too far back to point out some significant changes that have taken place in our industry over the past few years. Processes, materials, equipment, and board designs continue to change. If I were to pick one to focus on for this column, it would be in the ever-increasing trends toward higher circuit density. This relates to finer lines and spaces, smaller diameter blind vias, and even multilevel stacked and staggered vias. All of these changes will continue to place significant pressures on bare PCB fabricators to increase their investment and onboard new and critical skill sets.
What Is Driving These Changes?
The semiconductor packaging industry is driving changes to higher density for both the bare board as well as IC substrates, system integration, SiP, and very large-scale integration (VLSI). Increased device complexity has been a primary driving factor for future designs. To keep the component package size small, component lead spacing was decreased. Further increases in semiconductor integration (VLSI), requiring more than 196 I/Os, can drive packages to even closer perimeter lead spacing such as 0.5 mm, 0.4 mm, 0.3 mm, and 0.25 mm. The array package format has become standard for high I/O count devices. To support these requirements, wiring density is increased.
To read this entire column, which appeared in the November 2019 issue of PCB007 Magazine, click here.