03-28-2023

In last month's column, this author framed up the initial challenges for the PWB fabricator to be successful in producing IC substrates to support advanced packaging. In this month’s feature, the author will explore two more areas of processing that fabricators need to master: Imaging/developing, and etching.

03-07-2023

There has been much written and discussed over the last 18 months relating to semiconductor fabrication and the well-founded concerns that the U.S., in particular, has fallen behind in domestic chip manufacturing. In response to this issue, the United States government has enacted the CHIPS for America Act. Funding under this legislation is designed to drive more chip fabrication domestically. While this is all fine and good, once these advanced chips are manufactured, where will they go? As has been said ad nauseum, “Chips don’t float.”

01-09-2023

As circuits become more compact, circuit lines and the spaces between them are becoming finer. As the distances between these lines decrease, copper over-plating is more likely to have a deleterious effect on photoresist stripping, which can lead to shorts on costly fine-line PCBs. PCB designers, for example, must attempt to squeeze increasingly more amounts of information onto a smaller board. In practical terms, this means that circuits are becoming more compact; circuit lines and the spaces between them are becoming finer. As the distances between these lines decrease, copper overplating is more likely to have a deleterious effect on photoresist stripping.

11-09-2022

The photolithography process defines the circuitry on the panel. As one may surmise, the imaging process used in the fabrication of high density and ultra high-density circuity has made significant advances over the last decade—and just in time. With finer lines and spaces as well as more attention to fabrication of printed wiring advanced packaging substrates. However, as is so true of many of the processes in PWB fabrication, up and down stream processes can and will influence what happens in a particular process.

10-06-2022

Success in the plating room rests largely on the understanding of and the application of those critical principles that govern the process of electrodeposition, or electroplating as it is often referred. This month, I look at the fundamentals of plating distribution and throwing power, and what that means for the circuit board fabricator. There are many factors that influence the flow of current in the electroplating cell and ultimately the distribution of the metal across the part along with the concept of throwing power.

08-15-2022

If one thought that electroless copper and other metallization systems were complex and the deep dark secrets of these systems shrouded in black magic, the discussions on electroplating will seem like brain surgery. In this next series of columns, the intricacies of electrodeposition technology and its function of building up the thickness of copper in the holes and on the surface will be presented in detail. Function of the active ingredients in the copper plating solutions will be presented. Process control limits for the various plating solution components and the effects on deposit integrity will be discussed.

03-04-2022

Electroplating a printed circuit board is by no means a trivial task. Higher layer counts, smaller diameter vias (through-hole and blind), as well as higher performance material sets contribute to the greater degree of difficulty with today’s technology. So, process engineers pay close attention to the “softer” issues such as cathode current density, solution chemistry (copper sulfate and sulfuric acid concentration), and—sometimes—addition agent control.

02-28-2022

It seems the operative word today is additive circuit board manufacturing, or for that matter, additive for everything. It is true that the use of additive manufacturing technology has found its way into different industries. While there may be several advantages to adopting additive technology in various industries, one should take a step back and truly assess where we are today in relation to conventional and advanced printed circuit board technology. It makes sense to understand the differences between fully additive, semi-additive, modified semi-additive (mSAP) and subtractive. In the end there are a number of options available to the fabricator and OEM to achieve high density and ultra-density circuitry to support higher end technologies including IC substrates.

02-02-2022

The photoimaging process is one of the first steps in the PCB fabrication process. In order to ensure that the image of the circuitry conforms as close to the desired design as possible (i.e. lines and spaces), surface preparation of the copper foil surface is one of the most critical success factors. Employing the optimum mix of surface cleaners and microetchants will provide a clean surface with sufficient surface area to promote dry film adhesion. The fabricator has numerous options and should determine the optimum process by accounting for the type of copper foil used as well as the classes of soils to be removed. More on copper foil types in a future column.

12-27-2021

One of the most difficult things about trouble shooting PCB defects is getting to and understanding the root cause of defects. Many of these defects have can have multiple origins. And many may not manifest themselves in the process where the defect occurred. Thus are the perils of jumping to conclusion about the defect. Often this author gets involved in solving technical issues and the engineer at the board fabricator or OEM calls the defect an anomaly. Not really a good idea to go off trivializing the “purported anomaly.” Failure to understand the true genesis of the defect will lead to incorrect remedies to these issues. We will now present some of these defects and the possible remedies.

10-25-2021

In a previous column, the author presented several options with which to accomplish blind and through-hole via filling. In this edition of “Trouble in Your Tank,” filling blind and through holes with polymeric pastes will be presented.

10-07-2021

For this month’s edition, we are taking a slightly different approach—that of presenting an actual case study. However, the basic principles of these columns continue.

08-24-2021

Regardless of the industry where one competes, there is constant pressure to develop new products and penetrate new markets. This difficulty is heightened when your company is situated in a high-technology industry such as electronics, which requires continuous investment in equipment, infrastructure, processes and, of course, skilled workers.

08-13-2021

Columnist Michael Carano speaks frankly about the current state of price increases in the PCB industry, and what needs to change to stay alive.

05-27-2021

Columnists were asked to consider subjects such as optimizing business processes and strategy, process optimization, and training your team. From my view, developing critical thinking skills will help engineers troubleshoot technical issues and bring the issue to quick resolution, as this is certainly a good lead in to training your team.

04-26-2021

One of the most difficult things about trouble shooting PCB defects is getting to and understanding the root cause of defects. Many of these defects have can have multiple origins. And many may not manifest themselves in the process where the defect actually occurred.

03-29-2021

Troubleshooting process related defects is not as simple an exercise as we would like to believe. The printed wiring board fabrication process is a complex set of mechanical and chemical processes containing multiple steps. When even one of the process steps is not in control, end results can be disastrous. For now, the author presents a view of some defects that at first glance the origins are not obvious.

02-19-2021

Minimizing defects and improving yields is especially important as the technology is becoming ever so complicated, and additional focus must be placed on yield improvements. This is where process management and control must be front and center.

01-21-2021

While troubleshooting everyday processing issues, final etching touches on many downstream processes. These include surface preparation, imaging, and copper surface quality. There are concerns with the etching process itself and how process issues and operating parameters impact the circuit formation quality. In this month’s edition of “Trouble in Your Tank,” the subject of etch-outs, undercut, and linewidth reduction will be presented.

12-30-2020

In last month’s column, Michael Carano presented various etching defect causes related to equipment parameters. In this month’s column, he discusses various other causes that lead to etching defects.

11-20-2020

Sure, etching of copper foil has been in existence since before through-holes were mechanically drilled. However, as circuit density has evolved into finer and finer lines and spaces, the mechanical and chemical aspects of etching copper have evolved as well. Michael Carano provides an overview of the inner layer and outer layer etching process, including chemical and mechanical aspects of the process, different chemical formulations involved, and other unique aspects of each.

10-23-2020

One cannot underestimate the importance of surface preparation of the copper surface and its relationship to dry film adhesion. Michael Carano explains why chemical cleaning methods are favored over mechanical methods as long as copper removal rates are reduced and excessive surface roughness is avoided.

09-29-2020

For those associated with PCB fabrication, one of the biggest nightmares is often the infamous interconnect defect (ICD). Essentially, an ICD is a separation of the plating from the interconnect foil. In this column, Mike focuses on Type 1 ICD and D-sep.

08-29-2020

Mike Carano highlights electroless copper plating solutions, focusing on a copper formulation based on copper chloride, EDTA, formaldehyde, and sodium hydroxide.

08-11-2020

In Mike Carano's words, "In my April 2020 column in PCB007 Magazine, I incorrectly misrepresented the origins and causes of conductive anode filament (CAF) formation. This follow-up column will provide more insight and depth of knowledge on the CAF failure mode."

07-31-2020

Michael Carano discusses two interesting technical problems: the case of circuit open or etch-out, which will also include circuit width reduction related to undercut, and a defect that relates to extraneous copper remaining on the board. Both issues illustrate the complex nature of PWB troubleshooting and defect analysis.

06-15-2020

Defects may “manifest” or be detected in or after a specific operation within the PCB manufacturing process, but the underlying root cause may have occurred earlier in the process. In this column, Mike Carano focuses on several anomalies that may have their origins in process steps not normally recognized as the root cause of the issue.

05-15-2020

There are many reasons to get incredibly frustrated and confused when presented with complex issues related to the PCB fabrication process. Mike Carano reviews the concerns with the possibility of multilayer board delamination and the root cause or causes of the defect.

04-30-2020

Mike Carano explains how there are two additional concerns fabricators must understand and reconcile as the circuit technology continues on the high-density curve along with the plethora of new materials to meet the technological demands: conductive anode filament (CAF) formation and wicking.

12-15-2019

Michael Carano's father always said to him, "You should never stop learning," even when he was 40 years old. This lesson applies to the PCB manufacturing industry as well and is where constant learning and new skills development come into play. Mike introduces a few new things you can learn, both technical and soft skills.

12-12-2019

One does not have to look too far back to point out some significant changes that have taken place in our industry over the past few years. Processes, materials, equipment, and board designs continue to change. If I were to pick one to focus on for this column, it would be in the ever-increasing trends toward higher circuit density. This relates to finer lines and spaces, smaller diameter blind vias, and even multilevel stacked and staggered vias. All of these changes will continue to place significant pressures on bare PCB fabricators to increase their investment and onboard new and critical skill sets.

11-15-2019

In my previous column, I presented several options with which to accomplish blind and through-hole via filling. In this edition of “Trouble in Your Tank,” I will discuss filling blind vias and through-holes with polymeric pastes.

10-24-2019

Even though they are a smaller part of the circuit board industry, flex and rigid-flex circuits have been growing in popularity over the last decade, and for good reasons. These circuits are made to be thin, flexible, and durable. However, in addition to the opportunities that come with flex and rigid-flex circuits, there are also challenges. Find out more here.

09-11-2019

High-density interconnect (HDI) demands that vias that do not contain component leads be plugged with either a polymeric paste or electroplated copper. In this column series, Michael Carano talks about the technology drivers for via filling/plugging in the context of HDI.

08-06-2019

Copper deposit in the vias with electroless copper or alternatives, such as carbon-based direct plate processes to the vias, depends on process control, equipment design, and chemical parameters. When these are not in control, defects arise. In this installment of the column series, Mike Carano will talk about metallization for HDI blind via processing.

05-09-2019

Two often overlooked performance attributes for organic solderability preservatives (OSPs) are the organic film thickness and the topography of the copper after microetch. Film thickness up to an extent is critical. However, the copper topography and surface preparation also play a role. Thus, you should not overlook the critical nature of the overall OSP film thickness. Read on.

03-20-2019

If we have learned anything about moving into HDI manufacturing, it is that it takes a great deal of thought and discipline to be successful. Unfortunately, as the following bullet points delineate, all too often, the fabricator underestimates the scope of HDI and what this manufacturing strategy truly entails.

02-28-2019

Surface preparation and cleaning are essential aspects of metal finishing and PCB fabrication. The PCB fabricator has several processes that fit the broad category of cleaning and surface preparation. However, the organization needs additional studies to enhance the broad portfolio of products for their respective fitness for use in today’s technology.

02-12-2019

Yes, there is some art to the resist stripping operation. However, it is more about the science. In a future column, I will present process control methods for resist stripping as well as dive into additional troublesome activities related to the process.

11-21-2018

Photoresist stripping has become a complicated process due to many unique resist formulations on the market. The first part of this column series looks at some of the most common problems in photoresist stripping, and offers strategies on how to address them.

10-23-2018

It happens when you least expect it. You think you have all the process controls in place to prevent issues after etching, but either copper remains where there should be none or photoresist remains on the copper.

09-12-2018

It is a given that the zinc tail can have a negative impact on PTH thermal reliability. Therefore, it is best to understand how to minimize its formation, or at least provide a means to mitigate the negative effects of the zinc tail.

08-16-2018

In previous columns and elsewhere in literature, concerns about electroless copper peeling from polyimide material have been reported. The main concern with is the creation of a void caused by peeling or blistering.

08-09-2018

This edition of “Trouble in Your Tank” will elucidate the difficulty of root cause defect analysis when incorrect assumptions (and thus conclusions) are made. Further, it will illustrate that when proper tools are used to study the issue, additional data is gathered that supports the actual cause of the defect.

07-16-2018

Some type of cleaning and surface structuring is required in virtually every step of the printed circuit manufacturing process, from preparing the raw laminate for etch or plating resist to final assembly board cleaning before shipment. In this edition of “Trouble in Your Tank,” I will attempt to cover most of the general cleaning problems that can occur in any of these steps and, where possible, any problems unique to a specific manufacturing step.

05-25-2018

Several columns have been published in this space describing the origins of voids in the plated through-hole. However, not all voiding is caused by or has its genesis in the electroless copper (PTH metalization) process.

05-03-2018

In the first two columns in this series, the author presented two critical areas of the PCB fabrication process thought to contribute to the mouse bite and pitting defects seen in productionat a fabrication facility. In those first two parts, photoresist lamination and exposure parameters were investigated as to the possible root cause of the defects.

04-17-2018

Surface preparation and cleaning are essential aspects of metal finishing and printed circuit board fabrication. The printed circuit board fabricator has several processes that fit the broad category of cleaning and surface preparation in its toolbox. It is critical that the engineer carefully evaluates these methods and processes to determine the most effective way to optimize yields.

02-15-2018

In last month’s column, I introduced a case study that centered on plating pits and mouse bites. There were three areas in the process that raised concern as to the potential root cause of the defect. Of course, as with the case in all troubleshooting situations, it is best to look at the problem with wide open eyes. Just because one is looking at an issue that is visible after copper plating, this should not mean that is the only place to look. And this case study illustrates that point quite clearly.

12-01-2017

Most of the dielectric materials that are used to make printed circuit boards incorporate reinforcement into the resin system. Reinforcement usually takes the form of woven glass fiber. Woven fiberglass is just like any other cloth, made up of individual filaments that are woven together on a loom.

11-10-2017

In Part 1 of this series on the importance of rinsing, the author presented an overview of the critical aspects of rinsing as it applies to the overall quality of a printed circuit board, with considerable space devoted to water conservation. Thus, we now turn to how one can improve rinsing effectiveness without increasing water consumption and, by default, significant waste treatment costs.

08-23-2017

In the first part of a series of columns focused on microvias, the importance of adopting HDI technology as a strategic initiative for the PWB fabricator is presented. The major drivers for HDI are listed.

07-14-2017

In nearly every chemical process step in the PCB industry, rinsing is an immediate and required process step. Rinsing is typically a crucial step following a chemical process, and is thought to be one that requires little or no attention to function properly. However, problems caused by ineffective rinsing are responsible for many rejects, as well as huge operating costs in the waste treatment department.

05-16-2017

Inadequate or excessive desmear will lead to several PTH defects and failures. Resin smear, ineffective texturing of the resin, and even overly aggressive desmear will contribute to poor plating, adhesion failures and a myriad of other non-conforming defects. However, proper troubleshooting protocol dictates that the engineer also looks at drilling as the contributor to these and other defects.

05-09-2017

Follow good shop practices in terms of surface preparation, electroless copper plating thickness and resist developing parameters. Optimal surface preparation utilizing cleaners and micro-etches is critical to eliminating copperto-copper peeling. In addition, over- and underdeveloping create their own set of process constraints. Pay very close attention to developer pH, operating temperature and break point

03-16-2017

The process of forming a reliable solder joint between the component and the printed circuit board is paramount with respect to the manufacturing of robust circuit board assemblies.

02-23-2017

Metalizing materials such as polyimide used for flexible circuitry provides a significant challenge for process engineers. Conventional electroless copper systems often required pre-treatments with hazardous chemicals or have a small process window to achieve a uniform coverage without blistering.

02-23-2017

Electroplating a printed circuit board is by no means a trivial task. Higher layer counts, smaller-diameter vias (through-hole and blind) as well as higher-performance material sets contribute to the greater degree of difficulty with today’s technology.

12-27-2016

In this month’s installment of Trouble in Your Tank, I will further explore the critical drilling parameters required to drill a “good hole” and provide information on some little-known parameters required for this operation.

11-28-2016

In the extensive process of printed circuit board fabrication, one of the steps involves mechanically drilling through-hole vias. Via formation is then followed by desmear and metallization. The quality of the through-hole drilling process (and by inference the quality of the drilled through-hole) or lack thereof will also impact the desmear and metalization processes.

11-02-2016

Introduction Sometimes the problems can really get pretty ugly. One would assume these uglies would be easy to correct. But most often, solving such a problem requires a much deeper dig into the process.

10-13-2016

Sometimes the problems can really get pretty ugly. One would assume these uglies would be easy to correct. But most often, solving such a problem requires a much deeper dig into the process.

07-20-2016

Sometimes there is confusion among PCB engineers and quality managers as to what constitutes reliability. Some may say that reliability refers to avoiding PTH failures such as corner cracks or interconnect defects. Then there are those who subscribe to a wider range of failure criteria to determine whether or not the final product is reliable for long-term service.

06-14-2016

The proper development of the primary photoresist is critical to the overall success of the imaging process and in turn the processes that follow—either etching to form innerlayers or the electroplating processes on outer layers. In this step, the unexposed photoresist (after resist lamination and exposure) is washed away via the developing process.

05-14-2016

It is the job of the PCB process engineer to ensure that a quality circuit is delivered. This process starts with sound mechanics of the im-aging system that include surface cleanliness and resist lamination parameters.

05-18-2015

Getting the OSP process to perform as it is intended requires attention to both the equipment operating parameters as well as chemistry. This month's "Trouble in Your Tank" delves into one of the most irritating issues with respect to OSP: discoloration (read "oxidation") on critical circuit features.

04-21-2015

Many factors are in play when it comes to preventing ink from remaining in vias. In this article, Michael Carano presents two factors: solder not flowing in the vias and the lack of a plated solderable finish in the vias. This may be because some of the vias have a final finish in them and others do not--and all of these are happening on the same boards!

03-24-2015

Half-etch technology is production proven in meeting high density circuitry requirements. Thinner copper is effective in achieving sub-35 micron lines and spaces due to the total copper thickness that must be etched.

01-06-2015

In this case study, a PCB fabricator investigates the root cause of solderability defects on ENIG-processed circuits. It was determined that the fabricator, due to process errors, caused hyper-corrosion within the nickel deposit, which led to the defects.

12-23-2014

While next-generation OSP as a final finish has become the standard for lead-free compatible assembly, one should assume that any new OSP meets the criteria. A number of simple procedures may be followed to qualify any new OSP and ensure it is compatible with these higher assembly temperatures. Columnist Michael Carano takes a closer look.

12-02-2014

The aggressive nature of the ENIG process is a particular nuisance for some aqueous-based LPIs. Simply scrubbing the copper surface prior to soldermask application is often not an effective adhesion promotion mechanism for LPI and ENIG. Before exploring surface topography further, it is important to understand outside influences such as ENIG and its effect on adhesion.

12-02-2014

The aggressive nature of the ENIG process is a particular nuisance for some aqueous-based LPIs. Simply scrubbing the copper surface prior to soldermask application is often not an effective adhesion promotion mechanism for LPI and ENIG. Before exploring surface topography further, it is important to understand outside influences such as ENIG and its effect on adhesion.

11-11-2014

Understanding the interactions of the materials, oxide treatment, and the lamination process will help you get to the root cause failures in multilayer fabrication. When troubleshooting multilayer defects, it is necessary to understand the effect certain process parameters have on quality and reliability. Truly, the quality of a multilayer PCB (prior to desmear/metallization) will depend on several factors presented in this column.

11-11-2014

Understanding the interactions of the materials, oxide treatment, and the lamination process will help you get to the root cause failures in multilayer fabrication. When troubleshooting multilayer defects, it is necessary to understand the effect certain process parameters have on quality and reliability. Truly, the quality of a multilayer PCB (prior to desmear/metallization) will depend on several factors presented in this column.

09-23-2014

Ideally, the ENIG process must provide the optimum in solder joint reliability while operating at the highest level of cost efficiency. All too often, process parameters that have the most influence on these critical attributes are poorly understood.

09-23-2014

Ideally, the ENIG process must provide the optimum in solder joint reliability while operating at the highest level of cost efficiency. All too often, process parameters that have the most influence on these critical attributes are poorly understood.

09-11-2014

Columnist Michael Carano writes, "It is all about optimizing the performance of the oxide alternative chemistry. This includes close monitoring of the main reactive ingredients of the process chemistry. And one of the first issues that the industry had to address, whether one is using reduced oxide chemistry or oxide alternatives, is pink ring."

08-12-2014

Columnist Michael Carano presents additional information about nickel hyper-corrosion, a spike or fissure in the nickel deposit evident after immersion gold plating, by further defining the five degrees of hyper-corrosion. He also explores the root causes of such attacks on the base nickel along with strategies to mitigate these effects.

06-19-2014

The basic fundamentals of PTH drilling revolve around several key factors: 1) speeds and feeds--drill in-feed rate and spindle speed of the drill bit; 2) surface feet per minute; and 3) the material to be drilled. Understanding and applying these first few critical factors will influence the overall quality of the drilled, plated through-hole.

12-10-2013

Circuit designs with three-mil lines and spaces are increasingly becoming the norm. Optimizing the imaging process should be of paramount concern. Over the next few months, Mike Carano will present the critical steps in the imaging process and provide insight as to where potential yield reducing defects can occur and how to prevent them.

10-29-2013

In Part 1 and 2 of this series, Columnist Michael Carano presented critical information on ink properties, methods of soldermask application, tack drying, and more. In Part 3, the exposure process is detailed, including exposure units, UV lamps, the phototool, and overall exposure energy.

10-22-2013

In past columns, Michael Carano presented information about the different types of ICD interconnect defect and its root causes. One key defect that was not discussed is the infamous D-sep. What exactly is D-sep? Carano will explore this issue and provide suggestions for process improvement so you don't experience D-sep on your expensive, high-reliability PCBs.

09-24-2013

Achieving a void-free deposit through the PTH line need not be an elusive goal. Instead, careful thought should be given to line design and the critical interactions of chemical parameters. In addition, the fabricator and supplier must work closely to ensure high-performance materials can be processed with the highest levels of reliability.

08-26-2013

Both a reduced oxide process and an alternative oxide enhance the bond strength between the prepreg resin and the copper. In addition, the treated foil, if exposed by the wedge, is better able to stave off dissolution from the many acidic process steps to which the PWB will be subjected.

07-18-2013

The soldermask is an integral part of the circuit board. The proper application of soldermask requires strict attention to detail. This first article of a two-part series elucidates the critical operational requirements of the photoimageable soldermask process.

06-13-2013

Michael Carano writes, "I'm sure you've heard the words, 'It's not rocket science.' Apologies to the rocket scientists, but sometimes PCB fabrication just makes it look that way. This column approaches soldermask adhesion using an actual case study."

06-03-2013

Negative etchback is not a non-conforming defect according to IPC-600 (within limits). Acceptable levels of negative etchback do exist; however, there is a downside that can affect the overall plating quality in the PTH.

05-21-2013

This case study from Michael Carano emphasizes the critical thinking required to solve complex technical issues related to innerconnect defect. The defect described relates to drilling and inadequate drill smear removal, as opposed to plating as the root cause of the innerplane separation.

01-18-2013

With increased growth rates for HDI, lesser known technologies are being adopted, including three critical solderable finish processes: Acid copper superfilling of blind vias, paste interconnect, and direct electroless palladium over copper.

12-11-2012

Soldermask can peel or lift off areas on a PCB for a variety of reasons. This edition of "Trouble in Your Tank" presents the causes of soldermask peeling and lifting and stresses the importance of surface preparation prior to mask application.

09-22-2011

In previous columns related to the electroless nickel-immersion gold process, Michael Carano focused on plating and process defects related to mostly pre-plate process steps such as poor or inadequate cleaning, micro-etching and rinsing. This month, he tackles additional annoyances that lead to scrap and reduce the confidence in the ENIG process.