As IC die sizes continue to compact due to demand for smaller and faster technology, and as switching speeds continue to improve, rise and fall times are creeping down into the sub-nanosecond realm, a territory previously reserved for microwave engineers. This relentless shrinking trend that perpetuates Moore’s Law can create a huge problem for legacy designs as faster switching intensifies signal integrity issues. Over the years, as logic drivers have continued to switch faster and faster, problems with ringing, crosstalk and electromagnetic emissions (EMI) have become progressively worse.
It is a common quandary that established products that have worked flawlessly for years suddenly stop performing reliably, due to a new batch of ICs that is used in the latest production run. The cause of this problem is rise time shrinkage. Figure 1 illustrates the consequences of three different rise times for the same clock frequency.
Figure 1: Increased ringing with faster rise times (simulated in HyperLynx).
This example brings home two very important points. Firstly, for a given layout, faster switching produces spurious signals exhibiting excessive overshoot and ringing. This problem is unavoidable. It can only be prevented, to some extent, by improving the layout and routing, reducing the number of loads and/or adding terminators. Secondly, IC manufacturers are not always doing us a favor when they begin shipping "new and improved'' logic circuits. When substituted into a legacy design, the increase in speed may buy nothing but headaches.
From the perspective of an IC manufacturer, shrinking a die is a winning proposition because the new chip is almost certain to meet or exceed its published specifications at a lower cost. However, from the perspective of the designer, shrinking a die, in an existing product design, can be a daunting prospect, because the new rising and falling edges are almost certain to switch considerably faster.
Faster edge rates mean reflections and signal quality problems. So, even when the package hasn’t changed and the clock speed hasn’t changed, a problem may exist for legacy designs. The enhancements in driver edge rates have a significant impact on signal quality, timing and crosstalk. This also has a direct impact on radiated emissions.
To read this entire column, which appeared in the August 2017 issue of The PCB Design Magazine, click here.