Quiet Power: How Much Signal Do We Lose Due to Reflections?

November 18, 2019 | Istvan Novak, Samtec

We know that in the signal integrity world, reflections are usually bad. In clock networks, reflection glitches may cause multiple and false clock triggering. In medium-speed digital signaling, reflections will reduce noise margin, and in high-speed serializer/deserializer (SerDes) signaling, reflections increase jitter and create vertical eye closure.

Lee Ritchey on the Direction of PCB Design

November 14, 2019 | I-Connect007 Editorial Team

Editors Andy Shaughnessy and Nolan Johnson recently spoke with Lee Ritchey of Speeding Edge about the direction of PCB design. Lee also discusses some of the changes that he has seen in this industry over the past 40 years and some of the technological drivers that are causing designers to think more like electrical engineers than ever before.



Dana on Data: The DFM/Data Transfer Process Is Broken

November 14, 2019 | Dana Korf, Korf Consultancy LLC

In a world that is showing great strides toward implementing a Factory 4.0 world, why can’t a design be passed from a designer to the fabricator without errors every time? Dana Korf emphasizes moving the responsibility up in the...

The Digital Layout: Recent IPC DC Chapter Activities

October 23, 2019 | Stephen (Steph) Chavez, IPC Designers Council

We’re onto the second half of the year now, and we’ve seen lots of activities within our local Designers Council (DC) Chapters, including a few international chapters as well. Here's a snapshot of what has taken place so...

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