Cadence Releases UltraLink D2D PHY IP on TSMC N7, N6 and N5 Processes
August 24, 2020 | Business WireEstimated reading time: 2 minutes
Cadence Design Systems, Inc. announced the availability of its silicon-proven Cadence® UltraLink™ D2D PHY IP on the TSMC N7 process. Test silicon on the TSMC N7 process with full silicon characterization data is now available, an important milestone for very high-speed, advanced IP. Extensive silicon validation is necessary to guarantee design margins, performance across all process corners, bit-error rate (BER), insertion loss and maximum transmission speed. For the N6 process, re-characterized silicon data is available. Cadence is ready to engage with customers now with its UltraLink D2D PHY IP on the TSMC N7 and N6 processes. Cadence also recently taped out its UltraLink D2D IP on the TSMC N5 process and is now working with early adopter customers ahead of anticipated test silicon availability later this year.
System advances in accelerated computing platforms such as CPUs, GPUs and FPGAs, heterogeneous systems on chip (SoCs) for AI acceleration and high-speed networking/interconnects have all pushed chip integration to unprecedented levels. This requires more complex designs, larger die sizes and rapid adoption of the most advanced geometries. In order to manage the economics of advanced silicon and the ever-increasing monolithic die size, die-to-die connectivity has become increasingly important as multi-die designs using advanced packaging have become quite common.
“We’re pleased to see the result of our latest collaboration with Cadence in delivering Cadence’s D2D PHY IP across several TSMC advanced processes,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “This joint effort combining Cadence’s leading-edge SerDes IP and TSMC’s advanced process technologies helps our customers unleash their silicon innovations for emerging cloud computing, AI, 5G and hyperscale data center applications.”
“To help our mutual customers achieve success in advanced SoC designs for cloud computing applications, we’ve enabled our UltraLink D2D PHY IP in multiple TSMC advanced processes: First in N7 and N6, with a quick follow-on with N5 later this year,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “To address our customers’ rapidly evolving requirements, we continue to invest in both PAM4 and NRZ SerDes IP. The UltraLink D2D PHY IP is a critical technology delivering high bandwidth, low latency and power while enabling the proliferation of heterogeneous designs and integrated packaging solutions.”
The UltraLink D2D PHY IP delivers up to 40Gbps wire speed in an NRZ serial interface, providing up to 1Tbps/mm unidirectional bandwidth. While some existing lower speed die-to-die solutions require a silicon interposer to achieve the same bandwidth, the UltraLink D2D PHY IP offers significant cost advantages by supporting multi-chip modules on organic substrates. The IP extends Cadence’s broad high-performance computing (HPC) IP portfolio in support of the company’s Intelligent System Design™ strategy, enabling SoC design excellence.
Suggested Items
PCBflow Helps Designers Choose Best Manufacturer for the Job
03/28/2024 | Andy Shaughnessy, Design007 MagazineI recently spoke with a few technologists who have first-hand experience with PCBflow: Susan Kayesar, technical product manager with Siemens; Evgeny Makhline, CTO of Nistec, a CEM based in Israel; and Peter Tranitz, senior director of technology solutions and leader of the IPC Design Initiative. They explain how PCBflow functions, from the designer’s and manufacturer’s viewpoint, and how this database helps break down the wall between these stakeholders.
Elementary, Mr. Watson: Ensuring Design Integrity
03/28/2024 | John Watson -- Column: Elementary, Mr. WatsonBack in February, many of us watched the "Big Game." It reminded me of the saying, “It's not how you start that is important, but rather how you finish." It is perfectly okay when you are talking about sports, you get off to a bad first half and need to recover in the second half. However, when it comes to PCB design, this is not a good practice. If things start badly, they usually don't recover. They continue down that same path, costing more money and losing design time.
Arrow Electronics Launches Intelligent Vision Ecosystem
03/27/2024 | BUSINESS WIREArrow Electronics, Inc. is utilizing the onsemi Imager Access System (IAS) module standard for developing intelligent vision solutions for use in robotics, machine vision, commercial cameras and other uses.
Dymax Will Exhibit Light-Cure Solutions for Today’s Electronics at IPC APEX 2024
03/26/2024 | DymaxDymax, a leading manufacturer of rapid and light-curing materials and equipment, will exhibit at the IPC APEX EXPO 2024 in Anaheim, CA, April 9-11.
Synopsys Announces New AI-Driven EDA, IP and Systems Design Solutions At SNUG Silicon Valley
03/25/2024 | PRNewswireSynopsys, Inc. kicked off its annual flagship Synopsys User Group (SNUG) conference in Silicon Valley at the Santa Clara Convention Center with a keynote presentation by Synopsys president and CEO Sassine Ghazi. Ghazi discussed the unprecedented innovation opportunities and challenges that technology R&D teams face in this era of pervasive intelligence.