Sondrel Delivers Tape-out of Largest Chip Design
November 2, 2020 | SondrelEstimated reading time: 2 minutes
Sondrel has announced the tape-out of its largest chip design for a customer. This has taken a team of up to 200 engineers working on it simultaneously at times to design the 500 square millimetre chip that has over 30 billion transistors, 40 million flipflops, and 23 thousand pads for I/O, power and ground.
“This initially started out as a design for 28nm technology,” explained Stuart Vernon, Sondrel’s Senior Director of Physical Design. “However, it soon became apparent that, on 28nm, it would either be one very big chip, which would not have been cost effective, or it would have to be split into two connected chips, which would introduce parasitics and timing issues. So the decision was made to use the 16nm TSMC process node to enable the design to fit onto a single chip at a cost effective price point.”
Around a third of the floor plan of the chip is the block with the customer’s IP that handles the real-time image processing. Sondrel wrapped round that support blocks of Graphical Processor Unit, two Central Processor Units, on-chip cache memory, PCI and USB interfaces plus memory controllers to off-chip memory using over 7 kilometres of metal tracks on a chip the size of a postage stamp.
It would be impossible to design a chip of this complexity in one go as it has 300 million placeable logic cells and the placement tool can only handle 3 million at a time without the runtime becoming excessive. It was therefore divided into manageable-sized, functional blocks over four levels of a hierarchy structured like a pyramid. This enabled the design of the blocks to be divided between Sondrel teams that are located around the world. Once each block was finished, the big challenge was to bring them all together by creating abstract models of the lower blocks to provide input for the higher blocks so that the size of the part of design being implemented remained manageable. As the chip can run at up to 100 Watts, even the heat output of the different parts of the chip have to be allowed for in the design to prevent hotspots
Once all the component blocks had been implemented, the whole design was run as a complete unit on a dedicated computer farm consisting of 25 computers, each with 24 CPUs and 1.5 Terabytes of memory, and over 100 software licenses to perform physical validation checks, which took two days.
“We are one of the few digital design companies that can handle a design of this size and complexity, and we have several more nearing completion,” said Graham Curran, Sondrel’s CEO and Founder. “A key part of this is our experience of managing the logistics of having teams in seven different locations and co-ordinating their work. For example, our teams in India and China work in the evenings to maximise the overlap with our teams in Europe.”
Suggested Items
PCBflow Helps Designers Choose Best Manufacturer for the Job
03/28/2024 | Andy Shaughnessy, Design007 MagazineI recently spoke with a few technologists who have first-hand experience with PCBflow: Susan Kayesar, technical product manager with Siemens; Evgeny Makhline, CTO of Nistec, a CEM based in Israel; and Peter Tranitz, senior director of technology solutions and leader of the IPC Design Initiative. They explain how PCBflow functions, from the designer’s and manufacturer’s viewpoint, and how this database helps break down the wall between these stakeholders.
Elementary, Mr. Watson: Ensuring Design Integrity
03/28/2024 | John Watson -- Column: Elementary, Mr. WatsonBack in February, many of us watched the "Big Game." It reminded me of the saying, “It's not how you start that is important, but rather how you finish." It is perfectly okay when you are talking about sports, you get off to a bad first half and need to recover in the second half. However, when it comes to PCB design, this is not a good practice. If things start badly, they usually don't recover. They continue down that same path, costing more money and losing design time.
Arrow Electronics Launches Intelligent Vision Ecosystem
03/27/2024 | BUSINESS WIREArrow Electronics, Inc. is utilizing the onsemi Imager Access System (IAS) module standard for developing intelligent vision solutions for use in robotics, machine vision, commercial cameras and other uses.
Dymax Will Exhibit Light-Cure Solutions for Today’s Electronics at IPC APEX 2024
03/26/2024 | DymaxDymax, a leading manufacturer of rapid and light-curing materials and equipment, will exhibit at the IPC APEX EXPO 2024 in Anaheim, CA, April 9-11.
Synopsys Announces New AI-Driven EDA, IP and Systems Design Solutions At SNUG Silicon Valley
03/25/2024 | PRNewswireSynopsys, Inc. kicked off its annual flagship Synopsys User Group (SNUG) conference in Silicon Valley at the Santa Clara Convention Center with a keynote presentation by Synopsys president and CEO Sassine Ghazi. Ghazi discussed the unprecedented innovation opportunities and challenges that technology R&D teams face in this era of pervasive intelligence.