GBT Commences Research Project to Enhance Nanometer ICs Physical Verification Process
February 9, 2021 | Globe NewswireEstimated reading time: 3 minutes
GBT Technologies Inc., started a research project, internal name VeriSpeed, to develop new system and methods to enhance nanometer Integrated Circuits physical verification process.
A typical microchip design process involves few types of design’s verifications and validation. A design verification is the end-phase process to ensure that the integrated circuit works as planned. This process typically consumes vast amount of the total time spent on the microchip design. As microchips become more complex and advanced they include many more transistors and functions, all of which must be carefully tested and verified. A typical IC’s verification stages are functional design verification, which tests and validates the IC’s functionalities, physical design and verification, which checks the IC layout geometrical and electrical rules, packaging, and manufacturing tests.
During the physical design process a computer program is processing the microchip database, which is a huge size data. Typical processing of an advanced nanometer IC data, preparing it for physical verification, is a major time-consuming process. During this process the IC’s data is read and the program learns about the geometric shapes, which is called the mask layout. A set of mathematical algorithms then process this data to verify that all geometrical, electrical and DFM (Design For manufacturing) rules are met. The database engine is a key factor to the entire process performance.
VeriSpeed research project introduces a new approach to this essential element in this process, the IC’s data reading. By applying intelligent algorithms, the program will read the huge data according to a specific algorithm flow substantially speeding the entire verification process of nanometer and other Integrated Circuit’s layout Designs thus significantly impacting the global project’s design time cycle and manufacturing efficiency. The project aims to accelerate the entire IC’s verification process to enable reduction of total Integrated Circuit design time. This new database engine approach is targeted to work with GBT’s multiplanar methods as presented in the recent granted patent.
“We are seeking to introduce an intelligent key factor within the IC physical design and validation process by addressing probably the most significant part of it, the database processing. An efficient database engine is a key factor for speed and high performance of the entire physical verification process including its three main aspects. The DRC, Design Rules Check – Geometrical Rules, LVS - Layout Versus Schematic, the electrical rules, and DFM - Design for Manufacturing rules.” stated Danny Rittman the Company’s CTO
Based on advanced mathematical algorithm and deep learning the project will explore breakthrough approach and method for a new database engine that rapidly access to any specific area of the Integrated Circuit data. It is contemplated that the database engine will perform an initial analysis of the IC data to determine area’s priority for processing. The data then will be processed according to their density and complexity levels. The layout regions will be then processed in a fully hierarchical manner according to their internal indexing and priority weight.
In addition, unlike typical existing practice, it is expected that the proprietary mathematical algorithm will verify geometrical shapes in specific innovative method by split-and-merge segments to achieve higher speed. A neural network-based algorithm will validate the heuristic’s results to ensure on-track process. One of the main advantages of this system will be the early data process as the design moves forward. As the IC designer starts his/hers block design the system will learn the block’s data as the progresses. The database will be built incrementally over time and further shortened the final block physical verification process. The system will be working with GBT’s recent multiplanar 3D microchip methods as described in its patent.
Suggested Items
Elevating PCB Design Engineering With IPC Programs
04/24/2024 | Cory Blaylock, IPCIn a monumental stride for the electronics manufacturing industry, IPC has successfully championed the recognition of the PCB Design Engineer as an official occupation by the U.S. Department of Labor (DOL). This pivotal achievement not only underscores the critical role of PCB design engineers within the technology landscape, but also marks the beginning of a transformative journey toward nurturing a robust, skilled workforce ready to propel our industry into the future.
IPC Design Competition Champion Crowned at IPC APEX EXPO 2024
04/24/2024 | IPCAt IPC APEX EXPO 2024 in Anaheim, California, five competitors squared off to determine who was the best of the best at PCB design.
Altus Group Helps BitBox Unlock Productivity and Efficiency Gains with New Reflow Oven
04/22/2024 | Altus GroupAltus Group, a leading provider of capital equipment, has recently assisted BitBox, a UK-based electronics design, engineering and manufacturing company in upgrading its operations with the implementation of a new reflow oven from Heller Industries.
Real Time with... IPC APEX EXPO 2024: Exploring IPC's PCB Design Courses with Kris Moyer
04/18/2024 | Real Time with...IPC APEX EXPOGuest Editor Kelly Dack and IPC instructor Kris Moyer discuss IPC's PCB design training and education offerings. They delve into course topics such as design fundamentals, mil/aero, rigid-flex, RF design, and advanced design concepts. They also highlight material selection for high-speed design, thermal management, and dissipation techniques. The interview wraps up with details about how to access these courses online.
Cadence Unveils Palladium Z3 and Protium X3 Systems
04/18/2024 | Cadence Design SystemsThe Palladium Z3 and Protium X3 systems offer increased capacity, and scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models, ensuring proper functionality and performance.