Simultaneously Switching Noise: the Effect of the Power Distribution Network

Reading time ( words)

In the first installment of our blog series on Simultaneously Switching Noise, we went through an overview of SSN and explained its relevance to high-speed parallel busses such as DDR4. This time, we’ll be taking a closer look at the effects of a poorly designed Power Distribution Network (PDN) on SSN and signal integrity.

Effects of a poorly designed PDN

To illustrate the effects that a PDN can have on signals, consider a setup of a single DDR4 byte lane running at 2400Mt/s with each signal running a unique random sequence. In this simulation setup, the package capacitor is not loaded. This removal of a major source of power for the higher frequency transitions (artificially) exacerbates the SSN effect.

Figure 1: Poorly designed PDN

In Figure 1 above, the eye for DQ0 does not have a lot of margin around the eye mask. This is not a very good situation.

Bad PDN: Worst-Case Switching

We can see the situation get worse if instead of allowing each signal to have a unique random sequence, they all switched with the same sequence. This way, we can see the worst-case effects of SSN—that is, when all the signals are toggling in unison and placing a great deal of strain on the voltage rail.


Figure 2: Worst-case bit pattern with a poorly designed PDN

As can be seen in Figure 2, the eye for DQ0 gets a whole lot worse if all the bits are toggling with the same data pattern. In this case, this causes the eye to get closed.

Improving the PDN

Next, let’s insert the 4.7uF package capacitance which was removed to begin with. This should be a low-ESR capacitor and should be placed so that the inductance-causing loop area is minimized.


Figure 3: Worst-case bit pattern with improved PDN

In this setup, all the signals continue to toggle with the same bit-pattern. So, this is the worst-case situation with the package capacitor inserted. This DQ0 waveform in Figure 3, while better than that generated without the package capacitor in Figure 2, is only barely passing the eye mask.

In a more realistic situation, the signals would indeed be independent of each other. Using unique random bitstream for each signal, we get the DQ0 eye shown in Figure 4.


Figure 4: Unique, random bit patterns for all signals with improved PDN

The DQ0 eye improves dramatically. The smallest eye height in the mask region is now 275.5mV, better than the 211mV eye-height in the setup with the package capacitor where all the signals switch identically (Figure 3) and better than the 237mV eye-height with the setup where the package capacitors have been removed but the signals toggle independently of each other (Figure 1).

What we can gather from the above data is that the eye can be improved by adding appropriate package capacitors, or by ensuring that signals don’t all toggle identically. Ensuring that all the signals don’t toggle identically is one of the benefits of enabling the Data Bus Inversion (DBI) option in DDR4.

We will conclude the blog series next week by speaking more on the DBI option in DDR4. In the meantime, if you’d like to learn more about SSN and similar challenges, check out our white paper “DDR4 Board Design and Signal Integrity Challenges,” which was recently nominated for a DesignCon Best Paper Award.



Suggested Items

Keep Your Boards From Screaming with Eric Bogatin’s EMI Tips

01/26/2022 | Andy Shaughnessy, Design007 Magazine
I recently spoke with Eric Bogatin, the “signal integrity evangelist,” about his AltiumLive keynote presentation, “How to Keep Your Boards from Screaming Like a Banshee.” Eric explains how attention to board structures during the early stages of PCB layout can keep EMI from becoming a problem in your design. He also discusses a feature of Altium Designer that some designers may not know about—a 2D field solver that's part of the Simbeor high-end electromagnetic measurement tool, but with a simple GUI that most designers can master right away.

Why We Simulate

04/29/2021 | Bill Hargin, Z-zero
When Bill Hargin was cutting his teeth in high-speed PCB design some 25 years ago, speeds were slow, layer counts were low, dielectric constants and loss tangents were high, design margins were wide, copper roughness didn’t matter, and glass-weave styles didn’t matter. Dielectrics were called “FR-4” and their properties didn’t matter much. A fast PCI bus operated at just 66 MHz. Times have certainly changed.

Alternatives to Simulation

04/23/2021 | Dan Beeker, NXP Semiconductors
We are living in an age where the demands on electronic product designs are constantly evolving. The IC technology and operating speeds continue to pose significant challenges for teams as they work to develop their products. The increased transistor switching speeds and less forgiving compliance standards make signal integrity and electro-magnetic compliance more difficult to achieve. The status quo seems to have become, “We expect to fail EMC testing.”

Copyright © 2022 I-Connect007. All rights reserved.