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Happy’s Tech Talk #28: The Power Mesh Architecture for PCBsSiemens Introduces Questa Verification IP Solution Support for CXL 3.0 Protocol
August 30, 2022 | Siemens Digital Industries SoftwareEstimated reading time: 1 minute
Siemens Digital Industries Software announced that its simulator-independent Questa™ Verification IP solution now supports the new Compute Express Link (CXL) 3.0 protocol for high-performance computing (HPC) applications. CXL 3.0 is based on the Peripheral Component Interconnect Express (PCIe) networking protocol, which facilitates the rapid transfer of data between the world’s highest performance cloud computing servers as well as billions of smart connected devices around the world.
Available immediately, Siemens’ Questa Verification IP solution for CXL 3.0 integrates seamlessly into all advanced verification environments on any simulator. For customers looking to incorporate the new CXL 3.0 protocol into their next-generation designs, the solution helps customers optimize productivity and flexibility for the verification of block-level, subsystem, and system-on-a-chip (SoC) designs, which can speed time-to-market.
“By offering early support for the new CXL 3.0 protocol, Siemens can help customers differentiate and win in highly competitive HPC markets around the world,” said Mark Olen, product management director, IC Verification Solutions, Siemens Digital Industries Software. “Available now for early adopters of the CXL 3.0 protocol, our new Questa Verification IP solution provides a proven, robust and comprehensive verification platform that allows our customers to validate their next-generation designs with speed and confidence.”
Engineered to expedite verification closure and expose complex design issues, Siemens’ Questa™ Verification IP solution supports detailed functional verification across all layers of the CXL 3.0 specification. This latest offering from Siemens includes ready-to-use verification components and exhaustive stimuli that can help increase productivity and accelerate verification signoff. In addition, the solution can eliminate design biases found in many competing solutions.
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