Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity, Quality of Results
July 18, 2023 | Business WireEstimated reading time: 2 minutes
Cadence Design Systems, Inc. announced the delivery of the Cadence® Joules RTL Design Studio, a new solution that provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process. Front-end designers can access digital design analysis and debugging capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff. With this solution, users will also be able to leverage generative AI for RTL design exploration and big data analytics with Cadence’s leading AI portfolio. With Joules RTL Design Studio, users can achieve physical estimates quickly and accurately, unlocking up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL.
Joules RTL Design Studio expands upon Cadence’s existing Joules RTL Power Solution, addressing all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC). In addition, the new tool comes with a host of productivity-enhancing features and benefits, including:
One-of-a-kind intelligent RTL debugging assistant system: Provides early PPAC metrics as well as actionable debugging information throughout the design cycle—logical, physical, and production implementation—so engineers can explore “what-if” scenarios and potential resolutions to minimize iterations and improve design outcomes.
Based on proven engines: Joules RTL Design Studio shares the same trusted engines as the Innovus™ Implementation System, Genus™ Synthesis Solution, and Joules™ RTL Power Solution, enabling users to access all analysis and design exploration features from a single GUI for optimal QoR.
Powerful AI integrations: Joules RTL Design Studio has an integration with the generative-AI solution, Cadence Cerebrus™ Intelligent Chip Explorer, to explore design space scenarios, such as floorplan optimization and frequency versus voltage tradeoffs. Additionally, the Cadence Joint Enterprise Data and AI (JedAI) Platform allows trend and insight analysis across different versions of the RTL or across previous project generations.
Lint checker integration: Allows engineers to run lint checkers incrementally to rule out data and setup issues up-front, reducing errors and time to completion.
Unified cockpit: Provides RTL designers with an efficient, user-friendly experience, offering physical design feedback, localization and categorization of violations, bottleneck analysis and cross-probing between RTL, schematic, and layout.
“Now RTL designers can rapidly access all the physical information needed for PPAC debug without having to wait for implementation, which previously took days or weeks,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Joules RTL Design Studio gives designers visibility into the challenges when they can still be addressed easily, ultimately speeding time to market. Our early engagements reaffirmed our initial target of up to 5X faster RTL convergence and up to 25% improved QoR.”
Joules RTL Design Studio is part of the broader Cadence digital full flow, which provides customers with a faster path to design closure. The new tool and the broader flow support the company’s Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence.
Suggested Items
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.