-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current IssueBox Build
One trend is to add box build and final assembly to your product offering. In this issue, we explore the opportunities and risks of adding system assembly to your service portfolio.
IPC APEX EXPO 2024 Pre-show
This month’s issue devotes its pages to a comprehensive preview of the IPC APEX EXPO 2024 event. Whether your role is technical or business, if you're new-to-the-industry or seasoned veteran, you'll find value throughout this program.
Boost Your Sales
Every part of your business can be evaluated as a process, including your sales funnel. Optimizing your selling process requires a coordinated effort between marketing and sales. In this issue, industry experts in marketing and sales offer their best advice on how to boost your sales efforts.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - smt007 Magazine
Package-on-Package Warpage Characteristics and Requirements
July 25, 2016 | Wei Keat Loh, Intel Malaysia, and Haley Fu, iNEMIEstimated reading time: 3 minutes
Electronics packaging technology has been relentlessly changing and pushing design boundaries, leading to adoption of new materials, assembly processes, ultra-small geometries, and 2.5D and 3D integration. These changes have driven multiple assembly and surface mount challenges, and among these are concerns about package warpage. Current qualification criteria and standards are not adequate to predict good yield results at first- and second-level assemblies. Furthermore, measurement methods (dimensional and test) are neither common nor up-to-date.
The International Electronics Manufacturing Initiative (iNEMI) organized the Warpage Characteristics of Organic Packages Project to identify primary factors that can contribute to the warpage performance of selected components during typical SMT processes. The project team's plan was to define a qualification method and a set of criteria (e.g., sample size, precondition, variations of material and processes at the first and second levels) that could be used to evaluate warpage characteristics of new and existing packages in the design and manufacture of products. Their objective was to better understand package warpage characteristics across different package types and attributes. The project has, to date, evaluated several types of packages. This article focuses on the work related to package-on-package (PoP).
PoP is widely used in mobile devices due to its integrated design, lower cost and faster time to market. Understanding warpage characteristics and requirements of this type of package is critical to ensuring that both the top and bottom package can be mounted with minimal yield lost. The current state of PoP warpage requirements has not been reevaluated and formed in clear specification other than customer-specific requirements. The typical SMT defect modes, such as non-wet open, solder bridging, head and pillow, and non-contact open (Figure 1) are applicable to both the joints between the PoP bottom package with the board and the PoP memory package. Other gross SMT defects can occur when there are geometry interferences between the PoP packages. This shows there is a need for ensuring that the warpage between PoP bottom and memory package is compatible. Efforts to leverage the warpage character-such behavior. Eslampour, lists many measurement tools that can be used to measure the dynamic warpage of a package. The most common tool made available for this study was the thermal shadow moiré tool. The ability to measure warpage at elevated temperature provides better risk assessment for the formation of component board assembly joints. The common convention used to define the warpage direction is based on "+" and "–" magnitude which represent convex and concave direction. However, there are shapes that are hard to determine just using these two signs.
Figure 1: Typical SMT defect modes.
The measurement was conducted based on the availability of the sample and perceived risk level. There were three preconditioning considerations: "as is," "bake" and "MET" (manufacturing exposure time), listed in Table 2. The purpose of these considerations is to mimic potential conditions prior to board assembly.
'As is' mimics the potential condition where packages are directly mounted to the board after taken out of sealed bags without much staging time. 'Bake' mimics the condition where the package is baked after being staged for unknown condition prior to board assembly. The baking process potentially alters the stress state of the package and removes any diffused moisture. MET nine days mimics the condition where the package is being staged in the factory floor for nine days, exposed to 30°C and 60%RH prior to component board assembly process. The typical MSL 3 calls for a maximum seven days of staging, but the work here extended to nine days to take into account any unforeseen circumstances.
These three precondition environments may potentially demonstrate different package warpage behavior and board assembly yield depending on the packaging technology used. Due to uneven samples acquired, some package types listed here were not subjected to all these preconditions.
To read this entire article, which appeared in the July 2016 issue of SMT Magazine, click here.
Suggested Items
Taiyo Circuit Automation Installs New DP3500 into Fuba Printed Circuits, Tunisia
04/25/2024 | Taiyo Circuit AutomationTaiyo Circuit Automation is proud to be partnered with Fuba Printed Circuits, Tunisia part of the OneTech Group of companies, a leading printed circuit board manufacturer based out of Bizerte, Tunisia, on their first installation of Taiyo Circuit Automation DP3500 coater.
Vicor Power Orders Hentec Industries/RPS Automation Pulsar Solderability Testing System
04/24/2024 | Hentec Industries/RPS AutomationHentec Industries/RPS Automation, a leading manufacturer of selective soldering, lead tinning and solderability test equipment, is pleased to announce that Vicor Power has finalized the purchase of a Pulsar solderability testing system.
AIM Solder’s Dillon Zhu to Present on Ultraminiature Soldering at SMTA China East
04/22/2024 | AIMAIM Solder, a leading global manufacturer of solder assembly materials for the electronics industry, is pleased to announce that Dillon Zhu will present on the topic: Ultraminiature Soldering: Techniques, Technologies, and Standards at SMTA China East. This event is being held at the Shanghai World Expo Exhibition & Convention Center from April 24-25.
AIM to Highlight NC259FPA Ultrafine No Clean Solder Paste at SMTA Wisconsin Expo & Tech Forum
04/18/2024 | AIMAIM Solder, a leading global manufacturer of solder assembly materials for the electronics industry, is pleased to announce its participation in the upcoming SMTA Wisconsin Expo & Tech Forum taking place on May 7 at the Four Points by Sheraton | Milwaukee Airport, in Milwaukee, Wisconsin.
Hentec/RPS Publishes an Essential Guide to Selective Soldering Processing Tech Paper
04/17/2024 | Hentec Industries/RPS AutomationHentec Industries/RPS Automation, a leading manufacturer of selective soldering, lead tinning and solderability test equipment, announces that it has published a technical paper describing the critical process parameters that need to be optimized to ensure optimal results and guarantee the utmost in end-product quality.