Samsung, VeriSilicon Support Blaize AI Platform
October 28, 2020 | BlaizeEstimated reading time: 4 minutes
Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, in collaboration with design services provider, VeriSilicon, has successfully supported the on-time market launch of AI Edge computing startup Blaize’s hardware platform, despite the COVID-19 pandemic.
Leveraging Samsung Foundry’s 14nm FinFET process technology and VeriSilicon’s chip design expertise and IP, Blaize is now offering its AI Edge computing Pathfinder and Xplorer platforms equipped with the Blaize Graph Streaming Processor (GSP), bringing a new class of powerful AI compute capabilities to edge applications such as industrial, smart city, automotive sensor fusion, last mile delivery and retail.
Blaize, based in El Dorado Hills, Calif., is addressing a fundamental issue in Edge AI application deployment: existing solutions are either unable to handle the required computational load, or too costly and difficult to implement in products. At the heart of Blaize’s solution is a 100% programmable hardware platform that offers an unprecedented combination of low-latency AI processing, low energy demand, multi-sensor AI analytics, and an accompanying suite of software tools that greatly simplify and accelerate the AI development process.
“We built our architecture for Edge AI, rather than adapting it from designs developed for larger settings like data centers and Cloud applications,” explains Santiago Fernandez-Gomez, Blaize vice president of platform engineering. “Our customers are asking for solutions that are a fraction of the size, use much less power, and can be tailored to their specific market requirements.”
Blaize’s platform strategy implementation faced a critical challenge: quickly bringing a robust product to market. “For both technical and business reasons, our number one goal was to get into production and have products to sell, so we needed working GSP chips as soon as possible. That made a mature process node a top priority,” notes Fernandez-Gomez.
At the outset of Blaize’s engagement, Samsung Foundry assessed initial plans and goals for the GSP and recommended involving VeriSilicon, a one-stop source for custom silicon solutions and semiconductor IP, with an extensive track record including other AI-related projects.
“The Blaize GSP project is a perfect example of why Samsung Foundry has prioritized development of the Samsung Advanced Foundry Ecosystem (SAFE) partnership program, as we pursue our goal of delivering flawless execution,” states Hong Hao, senior vice president of Foundry Business at Samsung Electronics. “Providing well-integrated access to VeriSilicon’s design and IP expertise allows a young and innovative company like Blaize to leverage the full breadth and value of our leading process technologies in the most efficient way.”
“It is a compelling chip design, and the Blaize team has a very good technical background and competence in collaborating across multiple sites,” recalls Dr. Mahadev Kolluru, VeriSilicon’s vice president for North America platform solutions sales. An early order of business was selecting the optimal manufacturing process node; after evaluation of many options, Samsung Foundry’s 14nm FinFET process emerged as the ideal choice for this product.
“When we considered the target applications for the initial chip, and the fact that much of the required IP at the time was not yet available in more advanced nodes, the mature node made sense,” says Dr.
Kolluru. “Cost is always a concern for everyone. And given our experience working with Samsung on this process over the years, we were confident it was the best path to first-time silicon success.”
“In those initial few months, the Samsung Foundry team worked hand-in-hand with VeriSilicon, going through every possible design method that would give us the combination of performance and power consumption we required,” recalls Fernandez-Gomez. “The Samsung foundry brought solutions to the table beyond the standard flows that allowed us to fully meet out targets.”
Another key factor was effective supply chain planning. Despite the Covid-19 pandemic and global materials supply shortage, VeriSilicon was able to reserve production capacity not only with Samsung foundry but also with packaging, assembly, and test contractors.
The process rolled forward smoothly through 2019 and into 2020, with teams across locations working together in seamless fashion to address design challenges like system timing and integration of complex machine-learning IP blocks with the graphic-processing elements of the chip. VeriSilicon also provided a verification platform that allowed Blaize to begin developing drivers for the hardware platform. All systems were ready for scheduled tape-out in February when the global COVID-19 forced the lockdown of companies worldwide. VeriSilicon had to close offices 2 weeks before tape-out, but quickly adapted to working remotely along with the Blaize teams who were also transitioning to working remote, to deliver on the original target date.
Even better, when first silicon arrived, the samples were good enough to go directly into production. “In my experience,” adds Fernandez-Gomez, “it can often take six to nine months to go from first silicon to customer samples, and 12 to 18 months to a full production run. VeriSilicon delivered customer samples in two months and the silicon was pretty much perfect, and we will be in real production after six months.”
Samsung’s Hao calls the project “a success story that shows how a collaborative team effort can solve tough problems and meet ambitious goals. It is tremendously satisfying to work alongside people of the caliber found at Blaize and VeriSilicon, and to see so much knowledge and capability coming together in service of these exciting new Edge AI applications.”
Suggested Items
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.